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ST72324BJ2 Datasheet(PDF) 164 Page - STMicroelectronics

Part # ST72324BJ2
Description  8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
PDF  188 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72324BJ2 Datasheet(HTML) 164 Page - STMicroelectronics

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Electrical characteristics
ST72324B
164/188
Figure 84.
RAIN max. vs fADC with CAIN =0pF
(1)
1.
CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus
the pad capacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this,
fADC should be reduced.
Figure 85.
Recommended CAIN and RAIN values
(1)
1.
This graph shows that, depending on the input signal variation (fAIN), CAIN can be increased for
stabilization time and decreased to allow the use of a larger serial resistor (RAIN).
Figure 86.
Typical A/D converter application
tADC
Conversion time (Sample + Hold)
fCPU = 8 MHz, Speed = 0,
fADC =2MHz
7.5
µs
No. of sample capacitor loading cycles
No. of Hold conversion cycles
4
11
1/fADC
1.
Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k
Ω). Data
based on characterization results, not tested in production.
2.
Injecting negative current on adjacent pins may result in increased leakage currents. Software filtering of the converted
analog value is recommended.
Table 111.
10-bit ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0
5
10
15
20
25
30
35
40
45
010
30
70
CPARASITIC (pF)
2 MHz
1 MHz
0.1
1
10
100
1000
0.01
0.1
1
10
fAIN(KHz)
Cain 10 nF
Cain 22 nF
Cain 47 nF
CAIN
AINx
ST72XXX
VDD
VT
0.6V
VT
0.6V
CADC
12pF
VAIN
RAIN
10-bit A/D
conversion
2k
Ω (max)
Ilkg



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