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PIC18F6X2X Datasheet(PDF) 56 Page - Microchip Technology |
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PIC18F6X2X Datasheet(HTML) 56 Page - Microchip Technology |
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56 / 386 page  PIC18F6X2X/8X2X DS39612A-page 54 Advance Information 2003 Microchip Technology Inc. PREINC2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) n/a 58 PLUSW2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) - value of FSR2 offset by value in WREG n/a 58 FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 35, 58 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 35, 58 STATUS — — —N OV Z DC C ---x xxxx 35, 60 TMR0H Timer0 Register High Byte 0000 0000 35, 135 TMR0L Timer0 Register Low Byte xxxx xxxx 35, 135 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 35, 133 OSCCON — — — — — — —SCS ---- ---0 25, 35 LVDCON — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 35, 255 WDTCON — — — — — — —SWDTE ---- ---0 35, 269 RCON IPEN — —RI TO PD POR BOR 0--1 11qq 35, 61, 103 TMR1H Timer1 Register High Byte xxxx xxxx 35, 141 TMR1L Timer1 Register Low Byte xxxx xxxx 35, 141 T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 35, 141 TMR2 Timer2 Register 0000 0000 35, 144 PR2 Timer2 Period Register 1111 1111 35, 144 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 35, 144 SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 35, 183 SSPADD SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode. 0000 0000 35, 183 SSPSTAT SMP CKE D/A PS R/W UA BF 0000 0000 35, 176 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 35, 177 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 35, 187 ADRESH A/D Result Register High Byte xxxx xxxx 36, 242 ADRESL A/D Result Register Low Byte xxxx xxxx 36, 242 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 36, 235 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 36, 236 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 36, 237 CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte xxxx xxxx 36, 174 CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 36, 174 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 36, 159 CCPR2H Enhanced Capture/Compare/PWM Register 2 High Byte xxxx xxxx 36, 174 CCPR2L Enhanced Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 36, 174 CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 36, 159 CCPR3H Enhanced Capture/Compare/PWM Register 3 High Byte xxxx xxxx 36, 174 CCPR3L Enhanced Capture/Compare/PWM Register 3 Low Byte xxxx xxxx 36, 174 CCP3CON P3M1 P3M0 CCP3X CCP3Y CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000 36, 159 ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 36, 171 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 36, 249 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other Oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6X2X devices; always maintain these clear. 4: RG5 is available only if MCLR function is disabled in configuration. |
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