PIC18F6X2X datasheet(94/386 Pages) MICROCHIP

94 / 386 page

PIC18F6X2X/8X2X

DS39612A-page 92

Advance Information

 2003 Microchip Technology Inc.

INTCON2 REGISTER

R/W-1

RBPU

INTEDG0

INTEDG1

INTEDG2

INTEDG3

TMR0IP

INT3IP

RBIP

bit 7

bit 0

bit 7

RBPU: PORTB Pull-up Enable bit

= All PORTB pull-ups are disabled

= PORTB pull-ups are enabled by individual port latch values

bit 6

INTEDG0: External Interrupt 0 Edge Select bit

= Interrupt on rising edge

= Interrupt on falling edge

bit 5

INTEDG1: External Interrupt 1 Edge Select bit

= Interrupt on rising edge

= Interrupt on falling edge

bit 4

INTEDG2: External Interrupt 2 Edge Select bit

= Interrupt on rising edge

= Interrupt on falling edge

bit 3

INTEDG3: External Interrupt 3 Edge Select bit

= Interrupt on rising edge

= Interrupt on falling edge

bit 2

TMR0IP: TMR0 Overflow Interrupt Priority bit

= High priority

= Low priority

bit 1

INT3IP: INT3 External Interrupt Priority bit

= High priority

= Low priority

bit 0

RBIP: RB Port Change Interrupt Priority bit

= High priority

= Low priority

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

Note:

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state

of its corresponding enable bit or the global enable bit. User software should ensure

the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature

allows for software polling.

PIC18F6X2X Datasheet(PDF) 94 Page - Microchip Technology

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