P89CV51RB2FBC datasheet(29/73 Pages) NXP

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P89CV51RB2_RC2_RD2_1

Product data sheet

Rev. 01 — 5 October 2007

29 of 73

NXP Semiconductors

P89CV51RB2/RC2/RD2

80C51 with 1 kB RAM, SPI

6.5.1 Capture mode

In the Capture mode there are two options which are selected by bit EXEN2 in T2CON. If

EXEN2 = 0 Timer 2 is a 16-bit timer or counter (as selected by C/T2 in T2CON) which

upon overﬂowing sets bit TF2, the Timer 2 overﬂow bit. The Capture mode is illustrated in

Figure 11.

This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit ET2 in

the IE register). If EXEN2 = 1, Timer 2 operates as described above, but with the added

feature that a 1-to-0 transition at external input T2EX causes the current value in the

Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H,

respectively.

In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like

TF2 can generate an interrupt (which vectors to the same location as Timer 2 overﬂow

interrupt). The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to

determine which event caused the interrupt.

TCLK

Transmit clock ﬂag. When set, causes the UART to use Timer 2 overﬂow

pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1

overﬂows to be used for the transmit clock.

EXEN2

Timer 2 external enable ﬂag. When set, allows a capture or reload to occur

as a result of a negative transition on T2EX if Timer 2 is not being used to

clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

TR2

Start/stop control for Timer 2. A logic 1 enables the timer to run.

1C/T2

Timer or counter select. (Timer 2)

0 = internal timer (fosc /6)

1 = external event counter (falling edge triggered; external clock’s

maximum rate = fosc / 12)

CP/RL2

Capture/Reload ﬂag. When set, captures will occur on negative transitions

at T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with

Timer 2 overﬂows or negative transitions at T2EX when EXEN2 = 1. When

either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to

auto-reload on Timer 2 overﬂow.

Table 21.

T2MOD - Timer 2 mode control register (address C9H) bit allocation

Not bit addressable; reset value: XX00 0000B.

Bit

Symbol

T2OE

DCEN

Table 22.

T2MOD - Timer 2 mode control register (address C9H) bit description

Bit

Symbol

Description

7 to 2

Reserved for future use. Should be set to 0 by user programs.

T2OE

Timer 2 Output Enable bit. Used in programmable Clock-out mode only.

DCEN

Down Count Enable bit. When set, this allows Timer 2 to be conﬁgured as

an up/down counter.

Table 20.

T2CON - Timer/Counter 2 control register (address C8H) bit description …continued

Bit

Symbol

Description

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