P89CV51RB2FBC datasheet(13/73 Pages) NXP

13 / 73 page

P89CV51RB2_RC2_RD2_1

Product data sheet

Rev. 01 — 5 October 2007

13 of 73

NXP Semiconductors

P89CV51RB2/RC2/RD2

80C51 with 1 kB RAM, SPI

The DPTR points to location 0A0H and the data in the accumulator is written to address

0A0H of the expanded RAM rather than off-chip external memory. Access to EXTRAM

addresses that are not present on the device (above 2FFH) will access external off-chip

memory and will perform in the same way as the standard 8051, with P0 and P2 as

data/address bus, and P3[6] and P3[7] as write and read timing signals.

When EXTRAM = 0, MOVX @Ri and MOVX @DPTR will be similar to the standard 8051.

Using MOVX @Ri provides an 8-bit address with multiplexed data on Port 0. Other output

port pins can be used to output higher order address bits. This provides external paging

capabilities. Using MOVX @DPTR generates a 16-bit address. This allows external

addressing up to 64 kB. Port 2 provides the high-order eight address bits (DPH), and

Port 0 multiplexes the low-order eight address bits (DPL) with data. Both MOVX @Ri and

MOVX @DPTR generates the necessary read and write signals (P3[6] - WR and P3[7] -

RD) for external memory use. Table 7 shows external data memory RD, WR operation

with EXTRAM bit.

The stack pointer (SP) can be located anywhere within the 256 B of internal RAM (lower

128 B and upper 128 B). The stack pointer may not be located in any part of the expanded

RAM.

Table 6.

AUXR - Auxiliary function register (address 8EH) bit description

Bit

Symbol

Description

7 to 2

Reserved for future use. Should be set to 0 by user programs.

EXTRAM

Internal/external RAM access using MOVX @Ri/@DPTR. When 1,

accesses internal XRAM with address speciﬁed in MOVX instruction.

If address supplied with this instruction exceeds on-chip available

XRAM, off-chip RAM is accessed. When 0, every MOVX instruction

targets external data memory by default.

ALE off: disables/enables ALE. AO = 0 results in ALE emitted at a

constant rate of 1

⁄

2 the oscillator frequency. In case of AO = 1, ALE is

active only during a MOVX or MOVC.

Table 7.

External data memory RD, WR with EXTRAM bit

AUXR

MOVX @DPTR, A or MOVX A, @DPTR

MOVX @Ri, A or MOVX A, @Ri

ADDR < 0300H

ADDR

≥ 0300H

ADDR = any

EXTRAM = 0

RD/WR asserted

EXTRAM = 1

RD/WR not asserted

RD/WR asserted

RD/WR not asserted

P89CV51RB2FBC Datasheet(PDF) 13 Page - NXP Semiconductors

P89CV51RB2FBC Datasheet(HTML) 13 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

Datasheet Download

Link URL