P89CV51RB2FBC datasheet(63/73 Pages) NXP

63 / 73 page

P89CV51RB2_RC2_RD2_1

Product data sheet

Rev. 01 — 5 October 2007

63 of 73

NXP Semiconductors

P89CV51RB2/RC2/RD2

80C51 with 1 kB RAM, SPI

Fig 33. Shift register mode timing waveforms

002aaa552

ALE

instruction

valid

tXLXL

set TI

set RI

tXHQX

tQVXH

tXHDV

tXHDX

clock

output data

write to SBUF

input data

clear RI

Table 58.

SPI interface timing

Symbol

Parameter

Conditions

Variable clock

fosc =18MHz

Unit

Min

Max

Min

Max

fSPI

SPI operating frequency

Tcy(clk) / 4

MHz

TSPICYC

SPI cycle time

see Figure 34, 35, 36, 37

4Tcy(clk)

222

tSPILEAD

SPI enable lead time

see Figure 36, 37

250

tSPILAG

SPI enable lag time

see Figure 36, 37

250

tSPICLKH

SPICLK HIGH time

see Figure 34, 35, 36, 37

2Tcy(clk)

111

tSPICLKL

SPICLK LOW time

see Figure 34, 35, 36, 37

2Tcy(clk)

111

tSPIDSU

SPI data set-up time

master or slave;

see Figure 34, 35, 36, 37

100

tSPIDH

SPI data hold time

master or slave;

see Figure 34, 35, 36, 37

100

tSPIA

SPI access time

see Figure 36, 37

tSPIDIS

SPI disable time

see Figure 36, 37

160

tSPIDV

SPI enable to output data

valid time

see Figure 34, 35, 36, 37

111

tSPIOH

SPI output data hold time

see Figure 34, 35, 36, 37

tSPIR

SPI rise time

see Figure 34, 35, 36, 37

SPI outputs (SPICLK, MOSI,

MISO)

100

SPI inputs (SPICLK, MOSI,

MISO, SS)

2000

tSPIF

SPI fall time

see Figure 34, 35, 36, 37

SPI outputs (SPICLK, MOSI,

MISO)

100

SPI inputs (SPICLK, MOSI,

MISO, SS)

2000

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