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P89CV51RB2FBC Datasheet(PDF) 49 Page - NXP Semiconductors

Part # P89CV51RB2FBC
Description  8-bit 80C51 5 V low power 64 kB flash microcontroller with 1 kB RAM, SPI, 6-clock CPU with 6/12-clock peripherals
PDF  73 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

P89CV51RB2FBC Datasheet(HTML) 49 Page - NXP Semiconductors

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P89CV51RB2_RC2_RD2_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 5 October 2007
49 of 73
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
module’s CCAPnL SFR, the output will be LOW; when it is equal to, or greater, the output
will be HIGH. When CL overflows from FFH to 00H, CCAPnL is reloaded with the value in
CCAPnH. This allows the PWM to be updated without glitches. The PWM and ECOM bits
in the module’s CCAPMn register must be set to enable PWM mode.
6.9.5 PCA watchdog timer
An on-board watchdog timer is available with the PCA to improve the reliability of the
system without increasing chip count. Watchdog timers are useful for systems that are
susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA
module that can be programmed as a watchdog. However, this module can still be used
for other modes if the watchdog is not needed. Figure 24 shows a diagram of how the
watchdog works. The user pre-loads a 16-bit value in the compare registers. Just like the
other compare modes, this 16-bit value is compared to the PCA timer value. If a match is
allowed to occur, an internal reset will be generated. This will not cause the RST pin to be
driven HIGH.
User’s software then must periodically change (CCAP4H, CCAP4L) to keep a match from
occurring with the PCA timer (CH, CL). This code is given in the subroutine WATCHDOG
shown below.
In order to hold off the reset, the user has three options:
• Periodically change the compare value so it will never match the PCA timer.
• Periodically change the PCA timer value so it will never match the compare values.
• Disable the watchdog by clearing the WDTE bit before a match occurs and then
re-enable it.
The first two options are more reliable because the watchdog timer is never disabled as in
the third option. If the program counter ever reaches an undesired value, a match will
eventually occur and cause an internal reset. The second option is also not recommended
if other PCA modules are being used. Remember that the PCA timer is the time base for
all modules; changing the time base for other modules is not recommended. Thus, in
most applications the first option is best.
;CALL the following WATCHDOG subroutine periodically.
CLR
EA
;Hold off interrupts
MOV
CCAP4L,#00
;Next compare value is within 255 counts of
current PCA timer value
MOV
CCAP4H,CH
SETB
EA
;Re-enable interrupts
RET
Do not use this routine as part of an interrupt service routine, because if the program
counter would enter an infinite loop, still interrupts will be serviced and the watchdog will
continually keep getting reset. Because this would defeat the purpose of the watchdog, it
is recommended that this subroutine is called from the main program within 216 PCA timer
counts.



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