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TMP88CS38 Datasheet(PDF) 55 Page - Toshiba Semiconductor |
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TMP88CS38 Datasheet(HTML) 55 Page - Toshiba Semiconductor |
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55 / 226 page ![]() TMP88CS38/CM38A/CP38A 2007-09-12 88CS38-55 7 6 5 4 3 2 1 0 TBTCR (00036H) “0” − − “0” TBTEN TBTCK (Initial value: 0**0 0***) TBTEN Time base timer enable/disable 0: Disable 1: Enable NORMAL, IDLE mode DV1CK = 0 DV1CK = 1 000 fc/2 23 [Hz] fc/2 24 [Hz] 001 fc/2 21 fc/2 22 010 fc/2 16 fc/2 17 011 fc/2 14 fc/2 15 100 fc/2 13 fc/2 14 101 fc/2 12 fc/2 13 110 fc/2 11 fc/2 12 TBTCK Time base timer interrupt frequency select 111 fc/2 9 fc/2 10 Write only Note 1: fc: High-frequency clock [Hz], *: Don’t care Note 2: TBTCR is a write-only register and must not be used with any of read-modify-write instruction. Note 3: Set bit7 and 4 in TBTCR to “0”. Figure 2.3.2 Time Base Timer and Divider Output Control Register Table 2.3.1 Time Base Timer Interrupt Frequency (Example: at fc = 16 MHz) Time Base Timer Interrupt Frequency [Hz] NORMAL, IDLE mode TBTCK DV1CK = 0 DV1CK = 1 000 1.90 0.95 001 7.62 3.81 010 244.14 122.07 011 976.56 488.28 100 1953.12 976.56 101 3906.25 1953.12 110 7812.50 3906.25 111 31250 15625 |
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