AD4080BBCZ datasheet(32/94 Pages) AD

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Data Sheet

AD4080

DIGITAL INTERFACE

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Rev. A | 32 of 94

OVERVIEW

The AD4080 digital interface consists of a 4-wire SPI for device

configuration, four general-purpose input and output (GPIO) pins,

a conversion data access interface with selectable output format

(LVDS or SPI data interface), and a conversion start input (CNV+

and CNV−) that can be configures for LVDS or CMOS level signal-

ing.

The AD4080 configuration registers are accessed through the

SPI configuration interface (see the SPI Configuration Interface

section).

ADC Conversion Control

The ADC acquires a sample and initiates a conversion operation on

the rising edge of the convert start signal, applied at the CNV+ and

CNV− pins. There are two possible configurations for the electrical

signaling at the convert start input pins: CMOS or LVDS.

CMOS is the default mode on power up and after reset. CMOS

requires that the CNV− pin be tied to the digital interface ground

(IOGND). In this mode, the convert signal must be a CMOS logic

signal referenced to IOGND and applied at CNV+, with logic levels

according to the digital inputs (CNV, GPIOx, DCS, and DCLK)

parameters in Table 1.

To switch to LVDS mode, the LVDS_CNV_EN bit of the ADC Data

Interface Configuration B register (see the ADC Data Interface Con-

figuration B Register section, Address 0x16) must be set to 1. In

this mode, an external 100 Ω termination resistor must be installed

between the CNV+ and CNV− pins, as close to the AD4080 as

possible. In LVDS mode, the CNV+ and CNV− pins must be driven

differentially with an LVDS driver conforming to the levels specified

in the LVDS I/O (EIA-644) parameters in Table 1. Care must be

taken to closely match the CNV+ and CNV− differential signal pair

routing and to use controlled impedance to ensure signal integrity.

ADC Conversion Data Interface

Two signaling format options are available to access conversion

results:

►

LVDS level signaling (LVDS data Interface)

►

CMOS level signaling (SPI data interface)

The choice of interface is usually determined by the requirements

and constraints of the application at hand. For example, if contin-

uous fast data acquisition is required, then the LVDS signaling

interface is typically the preferred option. If the application requires

only noncontinuous bursts of data acquisitions, then either the

LVDS or the SPI data interfaces can be used. The capabilities of

the digital interface host can also determine which interface option

is chosen.

Common to both the LVDS and SPI data interfaces are the follow-

ing flexible features, which reduce the burden on the chosen digital

host:

►

Multilane data transfer: enables sustained data throughput at

reduced interface clock speeds.

►

Test pattern generation: facilitates interface integrity checks.

Additionally, for the LVDS only, there is the option to set a configu-

rable output drive.

By default, the LVDS interface is selected on power up and after a

reset. As can be seen in Figure 50, for LVDS, the data path of the

ADC results is routed though the offset and gain correction block

where there is the option to:

►

Continuously read, directly, the raw ADC conversion results.

►

Continuously read the ADC results processed by a user-selected

digital filter (see the Digital Filter section for details).

►

Read up to 16k unfiltered results from the FIFO.

►

Read up to 16k digitally filtered results from the FIFO.

Figure 50. LVDS Data Interface Options

If configured for the SPI data interface, as can be seen in Figure 51,

the available data paths are as follows:

►

Read up to 16k unfiltered results from the FIFO.

►

Read up to 16k digitally filtered results from the FIFO.

Figure 51. SPI Data Interface Data Path Options

Additional features specific to the selected interface format are also

available and are described in the LVDS Data Interface section and

the SPI Data Interface section.

SPI CONFIGURATION INTERFACE

All serial transactions between the system host and the AD4080

configuration registers are executed using the configuration SPI.

Each serial transaction consists of at least one instruction phase

during which the desired memory operation, that is, read or write,

AD4080BBCZ Datasheet(PDF) 32 Page - Analog Devices

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