AD4080BBCZ datasheet(67/94 Pages) AD

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Data Sheet

AD4080

DIGITAL FEATURES

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Rev. A | 67 of 94

Filter Result Ready Indicator

Setting the GPIO_x_SEL bits to 0011 configures the GPIO to output

the FILTER_RESULT_RDY signal, which is an active low logic

signal that indicates to the host controller when each new filter

result is complete. When LVDS is used to directly read out the filter

results, this indicator can alert the user when each new filtered

conversion result is available to read via the interface.

Filter Interface Timing Considerations

Continuous access to filtered data results is available only through

the LVDS data interface. SPI data interface access to filtered

results is only made via the FIFO. The timing considerations, in this

case, are described in the Filter Interface Timing Considerations

when Using the FIFO section. For use with the LVDS data interface,

it is recommended to use a GPIO, configured with the appropriate

GPIO_x_SEL (0011) to output the filter result ready (active low)

signal, as is shown in the example Figure 96 timing diagram.

Filter Interface Timing Considerations when

Using the FIFO

Figure 98 serves as an example to illustrate the sequence of events

in this mode of operation. This example illustrates a sinc1 filter with

a decimate by 2 setting, where three results (that is, WATERMARK

= 3) are configured to be stored in the FIFO. When using the

integrated digital filters with the FIFO, the filter must be reset prior

to each FIFO acquisition record. This reset must be given on the

first CNV rising edge, where the FILTER_SYNC signal must be

brought low at least 15 ns prior to the CNV edge and then released

at least 5 ns before the next rising edge. The first ADC result

is ready tMSB after the second CNV rising edge. This first ADC

result is latched into the filter on the third CNV rising edge. The

fourth CNV rising edge latches the second ADC result into the

digital filter. On the fifth rising edge, the first decimate by 2 result

is complete, which is indicated by the FILTER_READY signal going

active on the fifth rising edge. This first filtered result is loaded into

the FIFO on the sixth CNV rising edge. Because this example uses

WATERMARK = 3, when three filtered (that is, six core ADC results,

decimated by 2) results are loaded to the FIFO, the WATERMARK

is reached, and FIFO_FULL is asserted to indicate to the user that

a FIFO record is available to read via the configured data interface

(that is, the LVDS data lane(s) of the SPI data lane(s)). To initiate a

subsequent FIFO record acquisition of the filtered ADC results, the

user must start the whole sequence over, beginning again with the

reset of the digital filter by bringing the FILTER_SYNC signal low on

the first rising edge of CNV.

Figure 98. Description of Filter Timing with FIFO

SINC1 FILTER DECIMATE ×2

FIFO WATERMARK 3 (1, 2, 3)

CNV

FIFO_FULL

READ

VALID CNV COUNT

FILTER RESULT COUNT

FIFO COUNT

FILTER RESET IS REQUIRED

PRIOR TO INITIATING ACQUISTIONS

TO LOAD TO FIFO

FIFO FULL RETURNS

LOW AFTER FIRST RESULT

IS READ BY INTERFACE

INPUTS

OUTPUTS

INTERFACE

COUNTERS

CONTROL

SIGNALS

FILTER_SYNC

FILTER_RESULT_RDY

AD4080BBCZ Datasheet(PDF) 67 Page - Analog Devices

AD4080BBCZ Datasheet(HTML) 67 Page - Analog Devices

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