AD4080BBCZ datasheet(80/94 Pages) AD

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Data Sheet

AD4080

CONFIGURATION REGISTERS

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Interface Configuration C Register

Address: 0x10, Reset: 0x23, Name: INTERFACE_CONFIG_C

This register contains additional interface configuration settings.

Figure 122. Interface Configuration C Register

Table 45. Bit Descriptions for INTERFACE_CONFIG_C

Bits

Bit Name

Description

Reset

Access

[7:6]

CRC_ENABLE

CRC Enable. These bits are written to enable or disable the use of CRC on the interface. The

CRC_ENABLE bits must also be written to with the inverted value of these bits for the CRC to be

enabled.

0x0

R/W

0: CRC Disabled.

1: CRC Enabled.

STRICT_REGISTER_ACCESS

Multibyte Registers Must Be Read/Written in Full. When this mode is enabled, all bytes of a

multibyte register must be read/written in full.

0x1

R/W

0: Normal Mode. No access restrictions.

1: Strict Mode. Multibyte registers require all bytes accessed.

SEND_STATUS

Enables Sending of Status in 4-Wire Mode. When set, status information is sent by the device on

SDO during the instruction phase. When clear, no status is sent during the instruction phase.

0x0

R/W

[3:2]

ACTIVE_INTERFACE_MODE

Configuration SPI Mode. These bits are the active mode the SPI operates in.

0x0

[1:0]

CRC_ENABLE

Inverted CRC Enable. These bits must be written to with the inverted value of the CRC_ENABLE.

0x3

R/W

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