AD4080BBCZ datasheet(46/94 Pages) AD

46 / 94 page

Data Sheet

AD4080

DIGITAL INTERFACE

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Rev. A | 46 of 94

Self Clock Mode

In LVDS data interface mode, it is possible to disable the DCO+

and DCO− echo clock output (see the Echo Clock Mode section)

by setting LVDS_SELF_CLK_MODE = 1 in the ADC Data Interface

Configuration B register (see the ADC Data Interface Configuration

B Register section, Address 0x16). This setting puts the device

in self clock mode disabling the DCO+ and DCO− output driver,

with the benefit of saving interface power as well as reducing the

number of LVDS pairs required to interface with the host controller.

In this mode, the DCO+ and DCO− pins can be left disconnected;

therefore, in single-lane configurations, a minimum of two LVDS

pairs (CLK+ and CLK−, DA+ and DA−) are required to connect to

each AD4080 instance. The interface connectivity can further be

simplified by sharing the interface clock (CLK+ and CLK−) between

multiple AD4080 instances.

CNV+

CLK+

DA-

CNV-

CLK-

D10

[N-2]

D19

[N-1]

D18

[N-1]

D12

[N-1]

D11

[N-1]

D10

[N-1]

D19

[N]

D18

[N]

D17

[N]

D16

[N]

DA+

tCYC

tCNVH

tCNVL

tCCA

tCLK

tMSB_READ

tCLKD

Figure 75. Continuous Conversion Timing, LVDS Data Interface, Single Data Lane, Self Clock Mode

CNV+

CLK+

DA-

DB-

CNV-

CLK-

[N-2]

D19

[N-1]

D17

[N-1]

D15

[N-1]

D13

[N-1]

D11

[N-1]

D19

[N]

D17

[N]

D15

[N]

D13

[N]

DA+

[N-2]

D18

[N-1]

D16

[N-1]

D14

[N-1]

D12

[N-1]

D10

[N-1]

D18

[N]

D16

[N]

D14

[N]

D12

[N]

DB+

tCYC

tCNVH

tCNVL

tCCA

tCLK

tMSB_READ

tCLKD

Figure 76. Continuous Conversion Timing, LVDS Data Interface, Dual Data Lane, Self Clock Mode

AD4080BBCZ Datasheet(PDF) 46 Page - Analog Devices

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