AX88780 datasheet(28/55 Pages) ASIX

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AX88780

ASIX ELECTRONICS CORPORATION

0 = disable

UNICAST

R/W

Receive Directed Packet.

If this bit is enabled, AX88780 will compare the destination address

field of received packet with the address of MAC (refer to MACID0,

MACID1, MACID2).

When it is matched and good CRC, the packet

will be passed to driver. Otherwise it will be dropped.

1 = enable

0 = disable

MULTICAST

R/W

Receive all Multicast Packets.

If this bit is enabled, any multicast packet (good CRC) will be received

and passed to driver.

1 = enable

0 = disable

RXANY

R/W

Receive Anything.

If this bit is enabled, any packet whether it is good or fail will be

received and passed to driver.

1 = enable

0 = disable

4.29 MDIOCTRL--MDIO Control Register

Offset Address = 0xFC84

Default = 0x0000_0000

Field

Name

Type

Default

Description

31:16

All 0’s

Reserved

WTEN

R/W

Write Enable.

Driver enables this bit to issue a write cycle to PHY, it will be cleared when

finished the write cycle

1 = enable

0 = disable

RDEN

R/W

Read Enable.

Driver enables this bit to issue a read cycle to PHY. This bit will be cleared when

finished the read cycle

1 = enable

0 = disable

12:8

PHYCRIDX R/W

00000

PHY Register Index

If driver wants to access PHY, set this field to define the internal register index of

PHY.

7:5

000

Reserved

4:0

PHYID

R/W

00000

PHY ID

If driver wants to access PHY, set this field to define the address (ID) of PHY.

The address of internal PHY is fixed to 0x10

4.30 MDIODP--MDIO Data Port Register

Offset Address = 0xFC88

Default = 0x0000_0000

Field

Name

Type

Default

Description

31:16

All 0’s

Reserved

15:0

MDPORT R/W

All 0’s

PHY Data Port

To or from internal PHY data is put in this field.

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