AX88780 datasheet(29/55 Pages) ASIX

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AX88780

ASIX ELECTRONICS CORPORATION

4.31 GPIO_CTRL--GPIO Control Register

Offset Address = 0xFC8C

Default = 0x0000_0003

Field

Name

Type

Default

Description

31:10

All 0’s

Reserved

GPIO1S

R/W

GPIO1 Status

This bit stands for the pin status of GPIO1 when it is set to input mode.

1 = high state

0 = low state

GPIO0S

R/W

GPIO0 Status

This bit stands for the pin status of GPIO0 when it is set to input mode.

1 = high state

0 = low state

7:2

All 0’s

Reserved

GPIO1DIR R/W

GPIO1 Mode Direction

This field defines the direction of GPIO1 pin.

1 = input mode

0 = output mode

GPIO0DIR R/W

GPIO0 Mode Direction

This field defines the direction of GPIO pin.

1 = input mode

0 = output mode

Note: For output mode, software must firstly set the bit0 or bit1 to output mode then set bit8 or bit9.

4.32 RXINDICATOR--Receive Indicator Register

Offset Address= 0xFC90

Default = 0x0000_0000

Field

Name

Type

Default

Description

31:1

All 0’s

Reserved

RXSTART R/W

Receive Start

Driver set this bit to start or end receive operation from RX buffer of MAC.

1= Start read RX buffer

0= End read RX buffer

4.33 TXST--TX Status Register

Offset Address = 0xFC94

Default = 0x0000_0000

Field

Name

Type

Default

Description

31:4

All 0’s

Reserved

TXD3FAIL R

TX Descriptor3 Transmit Fail

When this bit is set 1, it means MAC fails in transmission of descriptor 3.

This bit will be self-cleared when driver reads TXST register.

TXD2FAIL R

TX Descriptor2 Transmit Fail

When this bit is set 1, it means MAC fails in transmission of descriptor 2.

This bit will be self-cleared when driver reads TXST register.

TXD1FAIL R

TX Descriptor1 Transmit Fail

When this bit is set 1, it means MAC fails in transmission of descriptor 1.

This bit will be self-cleared when driver reads TXST register.

TXD0FAIL R

TX Descriptor0 Transmit Fail

When this bit is set 1, it means MAC fails in transmission of descriptor 0.

This bit will be self-cleared when driver reads TXST register.

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