3.2

March 26, 2021

ES9016K2M Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-

8800 • www.esstech.com

4

PIN DESCRIPTIONS

Pin

Name

Pin Type

Reset

State

Pin Description

1

DGND

Ground

Ground

Digital Ground

2

N.C.

-

-

No internal connection. Pin may be grounded if desired.

3

SCL

I

Tri-stated

I2C Serial Clock Input

4

SDA

I/O

Tri-stated

I2C Serial Data Input/Output

5

ADDR

I

Tri-stated

I2C Address Select

6

XO

AO

Floating

XTAL Out

7

XI (MCLK)

AI

Floating

XTAL / MCLK In

8

N.C.

-

-

No internal connection. Pin may be grounded if desired.

9

DACR

AO

Driven to

ground

Differential Positive Analog Output Right

10

DACRB

AO

Driven to

ground

Differential Negative Analog Output Right

11

N.C.

-

-

No internal connection. Pin may be grounded if desired.

12

AGND

Ground

Ground

Analog Ground

13

DACL

AO

Driven to

ground

Differential Positive Analog Output Left

14

DACLB

AO

Driven to

ground

Differential Negative Analog Output Left

15

N.C.

-

-

No internal connection. Pin may be grounded if desired.

16

AVCCDAC

Power

Power

Analog AVCC for DAC

17

VCCA

Power

Power

Analog +1.8V or +3.3V for OSC

18

DVCC

Power

Power

Digital +1.8V to +3.3V

19

N.C.

-

-

No internal connection. Pin may be grounded if desired.

20

DGND

Ground

Ground

Digital Ground

21

DVDD

Power

Power

Digital Core Voltage, nominally +1.2V, is supplied by a regulator from

DVCC. DVDD must be decoupled with a minimum 4.7

F capacitor to

DGND for stable operation. DVDD needs to be externally supplied for

high XI / MCLK frequency. Please refer to the section about the DVDD

supply on page 7 for additional information.

22

N.C.

-

-

No internal connection. Pin may be grounded if desired.

23

N.C.

-

-

No internal connection. Pin may be grounded if desired.

24

GPIO1

I/O

Tri-stated

GPIO 1

25

DATA2

I

Tri-stated

DSD Data2 (R) or PCM Data CH1/CH2 or SPDIF Input 2

26

DATA1

I/O

Tri-stated

Master mode off: Input for DSD Data1 (L) or PCM Frame Clock or SPDIF

Input 3

Master mode on: Output for PCM Frame Clock

27

DATA_CLK

I/O

Tri-stated

Master mode off: Input for PCM Bit Clock or DSD Bit Clock or SPDIF

Input 1

Master mode on: Output for PCM Bit Clock

28

RESETB

I

Tri-stated

Master Reset / Power Down (active low)

Exposed

Pad

DGND

Ground

Ground

Digital Ground. Connect the Exposed Pad to DGND

Notes:

-

There are 7 N.C. (No Connect) pins. If desired, these pins can be connected to ground on the PCB to strengthen the

otherwise isolated pin pads.

-

The exposed pad must be connected to digital ground.