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ES9016K2M Datasheet(PDF) 10 Page - ESS Technology,Inc

Part # ES9016K2M
Description  Ultra 32-bit Stereo Low Power Audio DAC
PDF  38 Pages
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Manufacturer  ESS [ESS Technology,Inc]
Direct Link  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9016K2M Datasheet(HTML) 10 Page - ESS Technology,Inc

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3.2
March 26, 2021
ES9016K2M Datasheet
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-
8800 • www.esstech.com
10
SERIAL CONTROL INTERFACE
The registers inside the chip are programmed via an I2C interface. The diagram below shows the timing for this interface.
The chip address can be set to 2 different settings via the “ADDR” pin. The table below summarizes this.
ADDR
CHIP ADDRESS
0
0x90
1
0x92
Notes:
1.
The
“ADDR” pin is used to create the CHIP ADDRESS. (0x90, 0x92)
2.
The first byte after the chip address is the “ADDRESS” this is the register address.
3.
The second byte after the CHIP ADDRESS
is the “DATA” this is the data to be programmed into the register at the
previous “ADDRESS”.
Start
Start
Start
Stop
Parameter
Symbol
Standard-Mode
Fast-Mode
Unit
MIN
MAX
MIN MAX
SCL Clock Frequency
fSCL
0
100
0
400
kHz
START condition hold time
tHD,STA
4.0
-
0.6
-
s
LOW period of SCL
tLOW
4.7
-
1.3
-
s
HIGH period of SCL
tHIGH
4.0
-
0.6
-
s
START condition setup time (repeat)
tSU,STA
4.7
-
0.6
-
s
SDA hold time from SCL falling
tHD,DAT
0.3
-
0.3
-
s
SDA setup time from SCL rising
tSU,DAT
250
-
100
-
ns
Rise time of SDA and SCL
tr
-
1000
300
ns
Fall time of SDA and SCL
tf
-
300
300
ns
STOP condition setup time
tSU,STO
4
-
0.6
-
s
Bus free-time between transmissions
tBUF
4.7
-
1.3
-
s
Capacitive load for each bus line
Cb
-
400
-
400
pF



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