LMH2191

SNAS485D – JULY 2010 – REVISED MAY 2013

www.ti.com

LAYOUT RECOMMENDATIONS

As with any other device, careful attention must be paid to the board layout. If the board isn't properly designed,

the performance of the device can be less than desired. Care should be taken that the SCLK_IN input trace and

the output traces of CLK1 and CLK2 are as short as possible to reduce extra capacitive load observed by the

clock outputs. Also proper de-coupling close to the device is necessary. Table 1 depicts the advised component

values. TI suggests to use the evaluation board, available from the Texas Instruments web site www.ti.com, as a

guide for layout and as an aid in device testing and characterization.

Table 1. Recommended Component Values

Symbol

Parameter

Min

Typ

Max

Units

CBAT

(1)

Capacitor on VBAT

0.47

1

µF

COUT

(1)

Capacitor on VOUT

1

2.2

ESR

Equivalent Series Resistance

5

500

m

Ω

(1)

CBAT, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCC's) used in setting electrical characteristics.

14

Submit Documentation Feedback

Copyright © 2010–2013, Texas Instruments Incorporated

Product Folder Links: LMH2191