LMH2191

SNAS485D – JULY 2010 – REVISED MAY 2013

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3.5 V ELECTRICAL CHARACTERISTICS

(1) (continued)

Unless otherwise specified, all limits are specified at TJ = 25°C, VBAT = 3.5V, CBAT = 1µF, COUT = 2.2 µF

(2), f

SCLK_IN = 26 MHz,

IOUT = 1mA, Boldface limits apply at the temperature extremes.

Symbol

Parameter

Condition

Min(3)

Typ(4)

Max(3)

Units

CLK1

Additive Phase Noise

All outputs enabled at 26 f = 100 Hz

-128

Phase

MHz

f = 1 kHz

-144

Noise

f = 10 kHz

-150

f = 100 kHz

-160

f = 1 MHz

-163

All outputs enabled at

f = 100 Hz

-127

19.2 MHz

f = 1 kHz

-146

f = 10 kHz

-153

f = 100 kHz

-161

f = 1 MHz

-163

dBc/Hz

CLK2

Additive Phase Noise

All outputs enabled at 26 f = 100 Hz

-127

Phase

MHz

f = 1 kHz

-142

Noise

f = 10 kHz

-148

f = 100 kHz

-160

f = 1 MHz

-162

All outputs enabled at

f = 100 Hz

-129

19.2 MHz

f = 1 kHz

-144

f = 10 kHz

-151

f = 100 kHz

-163

f = 1 MHz

-164

V

OH

CLK1/2 Output Voltage High Level IOH = -2mA (equivalent output load

1.6

800

Ω)

V

V

OL

CLK1/2 Output Voltage Low Level

IOL = 2mA

0.2

ROFF

Ouput Impedance when disabled

with other output enabled (LDO

grounded

enabled)

Both outputs disabled (LDO disabled)

diode to ground

System Clock Input (SCLK_IN)

VI-pp

SCLK_IN peak- to- peak input

For duty cycle variation < 1%

0.6

1

1.8

V

level(7)

IIH

Current into SCLK_IN pin (Input

SCLK_IN = 1.8V, CLK_REQ1/2=Low

0

0.1

HIGH)

µA

IIL

Current into SCLK_IN pin (Input

SCLK_IN = 0V, CLK_REQ1/2=Low

–0.1

0

LOW)

CIN

Input Capacitance(8)

CLK_REQ1/2=High

7.5

13

pF

RIN

Input Resistance(8)

CLK_REQ1/2=High

14

20

k

Ω

see Application Note: Input Impedance

Switching Characteristics: System Clock Input

fSCLK_IN

System Clock

10

26

52

MHz

CLK_DC

Input Clock Duty Cycle

45

50

55

%

(8)

This parameter is specified by design and/or characterization and is not tested in production.

4

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