PCM1808

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SLES177B – APRIL 2006 – REVISED AUGUST 2015

9 Power Supply Recommendations

The PCM1808 device requires a 5-V nominal supply and a 3.3-V nominal supply. The 5-V supply is for the

analog circuitry powered by the VCC pin. The 3.3-V supply is for the digital circuitry powered by the VDD pin. The

decoupling capacitors for the power supplies should be placed close to the device terminals.

A VCC that varies from the nominal 5 V affects the reference voltage for the input. This has a slight impact on the

data conversion of the device.

10 Layout

10.1 Layout Guidelines

10.1.1 VCC, VDD Pins

Bypass the digital and analog power supply lines to the PCM1808 device to the corresponding ground pins with

both 0.1-

μF ceramic and 10-μF electrolytic capacitors as close to the pins as possible to maximize the dynamic

performance of the ADC.

10.1.2 AGND, DGND Pins

To maximize the dynamic performance of the PCM1808 device, there are no internal connections to the analog

and digital grounds. These grounds should have low impedance to avoid digital noise feedback into the analog

ground. They should be connected directly to each other under the PCM1808 device package to reduce potential

noise problems.

10.1.3 VINL, VINR Pins

VINL and VINR are single-ended inputs. These inputs have integrated antialias low-pass filters to remove the

high-frequency noise outside the audio band. If the performance of these filters is not adequate for an

application, the application requires appropriate external antialiasing filters. An appropriate choice would typically

be a passive RC filter in the range of 100

Ω and 0.01 μF to 1 kΩ and 1000 pF.

10.1.4 VREF Pin

To ensure low source impedance of the ADC references, the recommended capacitors between VREF and AGND

are 0.1-

μF ceramic and 10-μF electrolytic. These capacitors should be located as close as possible to the VREF

pin to reduce dynamic errors on the ADC references.

10.1.5 DOUT Pin

The DOUT pin has a large load-drive capability, but if the DOUT line is long, a recommended practice is to locate

a buffer near the PCM1808 device and minimize load capacitance to minimize the digital-analog crosstalk and

maximize the dynamic performance of the ADC.

10.1.6 System Clock

The quality of the system clock can influence dynamic performance, as the PCM1808 device operates based on

a system clock. Therefore, it may be necessary to consider the system clock duty, jitter, and the time difference

between system clock transition and BCK or LRCK transition in slave mode.

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Product Folder Links: PCM1808