SCKI

0.8 V

SCKI

2 V

t w(SCKL)

t w(SCKH)

PCM1808

www.ti.com

SLES177B – APRIL 2006 – REVISED AUGUST 2015

6.6 Timing Requirements

MIN

NOM

MAX

UNIT

SYSTEM CLOCK TIMING

tw(SCKH)

System clock pulse duration, HIGH

8

ns

tw(SCKL)

System clock pulse duration, LOW

8

ns

System clock duty cycle

40%

60%

CLOCK-HALT POWER-DOWN AND RESET TIMING

t(CKR)

Delay time from SCKI halt to internal reset

4

µs

t(RST)

Delay time from SCKI resume to reset release

1024 SCKI

µs

t(REL)

Delay time from reset release to DOUT output

8960 / fS

µs

AUDIO DATA INTERFACE TIMING (Slave Mode: LRCK and BCK Work as Inputs)(1)

t(BCKP)

BCK period

1 / (64 fS)

ns

t(BCKH)

BCK pulse duration, HIGH

1.5 × t(SCKI)

ns

t(BCKL)

BCK pulse duration, LOW

1.5 × t(SCKI)

ns

t(LRSU)

LRCK setup time to BCK rising edge

50

ns

t(LRHD)

LRCK hold time to BCK rising edge

10

ns

t(LRCP)

LRCH period

10

µs

t(CKDO)

Delay time, BCK falling edge to DOUT valid

–10

40

ns

t(LRDO)

Delay time, LRCK edge to DOUT valid

–10

40

ns

tr

Rise time of all signals

20

ns

tf

Fall time of all signals

20

ns

AUDIO DATA INTERFACE TIMING (Master Mode: LRCK and BCK Work as Outputs)(2)

t(BCKP)

BCK period

150

1 / (64 fS)

2000

ns

t(BCKH)

BCK pulse duration, HIGH

65

1200

ns

t(BCKL)

BCK pulse duration, LOW

65

1200

ns

t(CKLR)

Delay time, BCK falling edge to LRCK valid

–10

20

ns

t(LRCP)

LRCK period

10

1 / fS

125

ns

t(CKDO)

Delay time, BCK falling edge to DOUT valid

–10

20

ns

t(LRDO)

Delay time, LRCK edge to DOUT valid

–10

20

ns

tr

Rise time of all signals

20

ns

tf

Fall time of all signals

20

ns

AUDIO CLOCK INTERFACE TIMING (Master Mode: BCK Work as Outputs)(3)

t(SCKBCK)

Delay time, SCKI rising edge to BCK edge

5

30

ns

(1)

Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Rise and fall times are from 10% to 90% of the input-

output signal swing. Load capacitance of DOUT is 20 pF. t(SCKI) is the SCKI period.

(2)

Timing measurement reference level is 0.5 VDD. Rise and fall times are from 10% to 90% of the input-output signal swing. Load

capacitance of all signals is 20 pF.

(3)

Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Load capacitance of BCK is 20 pF. This timing applies

when SCKI frequency is less than 25 MHz.

Figure 1. System Clock Timing

Copyright © 2006–2015, Texas Instruments Incorporated

Submit Documentation Feedback

7

Product Folder Links: PCM1808