TMS470MF06607 datasheet(30/65 Pages) TI2

30 / 65 page

TMS470MF06607

SPNS157C

– JANUARY 2012

www.ti.com

3.12 Device Identification Code Register

The device identification code register identifies the coprocessor status, an assigned device-specific part

number, the technology family (TF), the I/O voltage, whether or not parity is supported, the levels of flash

and RAM error detection, and the device version. The TMS470M device identification code base register

value is 0X00246D15 and is subject to change based on the silicon version.

CP15

PART NUMBER

R-0

R-00000000010010

R-0

I/O VOLT

FLASHECC

RAMECC

R-011

R-0

R-1

R-10

R-1

VERSION

R-0010

R-1

R-0

R-1

LEGEND: R = Read only; -n = value after reset

Figure 3-4. TMS470M Device ID Bit Allocation Register

Table 3-13. TMS470M Device ID Bit Allocation Register Field Descriptions

Bit

Field

Value

Description

CP15

This bit indicates the presence of coprocessor (CP15).

No coprocessor present in the device.

Coprocessor present in the device.

30-17

PART NUMBER

These bits indicate the assigned device-specific part number.

The assigned device-specific part number for the TMS470M device is 00000000010010.

16-13

Technology family bit.

These bits indicate the technology family (C05, F05, F035, C035).

0011

F035

I/O VOLT

I/O voltage bit.

This bit identifies the I/O power supply.

3.3 V

5 V

Peripheral parity bit.

This bit indicates whether parity is supported.

No parity on peripheral.

Parity on peripheral.

FLASHECC

Flash ECC bits.

These bits indicate the level of error detection and correction on the flash memory.

No error detection/correction.

Program memory with parity.

Program memory with ECC.

Reserved

RAMECC

RAM ECC bits.

This bit indicates the presence of error detection and correction on the CPU RAM.

RAM ECC not present.

RAM ECC present.

7-3

VERSION

These bits identify the silicon version of the device.

2-0

101

Bits 2:0 are set to 101 by default to indicate a platform device.

Device Configuration

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