TMS470MF06607 datasheet(38/65 Pages) TI2

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Start Oscillator

Update Status and Prepare

for Normal Operation

Wake up

oscillator

Wake up

CPU

Wake up

VREG

8 MHz

OFF

Crystal-

Oscillator

with PLL

On-Chip

VREG

e.g., CAN

Module

CPU

Startup to Normal Operation

~2 ms, depending on xtal

Ready for Normal Operation/CAN Message

TMS470MF06607

SPNS157C

– JANUARY 2012

www.ti.com

5.1.2

Sequence to Wake Up from Sleep Mode

In sleep mode, all the clocks are turned off: HCLK, GCLK, VCLK, VCLK2, and RTICLK. All the clock

sources are also disabled. For more details on sleep mode, see the TMS470M Series Technical

Reference Manual (SPNU495). Sleep mode is not supported if the internal voltage regulator is disabled.

The wake-up options are: external interrupts via GIO pins, CAN, and SCI/LIN. The sequence for waking

up from the sleep mode is described below:

1. Wake-up request is received/generated. Figure 5-4 shows the CAN module generating the wake-up

interrupt based on a message received.

2. This wake-up event causes the on-chip VREG to wake up.

3. Once the on-chip VREG wakes up, the CPU and the main oscillator start to wake up.

4. Once the main oscillator output is valid, the software runs using the main oscillator as the clock source.

The software can prepare for normal operation. Also, now the PLL can be enabled.

5. Once the PLL has acquired LOCK, the software can switch over to using the PLL output clock for

normal operation.

Figure 5-4. Wake Up From Sleep Mode

Peripheral Information and Electrical Specifications

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