TMS470MF06607 datasheet(56/65 Pages) TI2

56 / 65 page

TMS470MF06607

SPNS157C

– JANUARY 2012

www.ti.com

5.7

Multi-Buffered A-to-D Converter (MibADC)

The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that

enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could

be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are

given with respect to ADREFLO unless otherwise noted.

Resolution

10 bits (1024 values)

Monotonic

Assured

Output conversion code

00h to 3FFh [00 for VAI ≤ ADREFLO; 3FF for VAI ≥ ADREFHI]

Table 5-22. MibADC Recommended Operating Conditions(1)

MIN

MAX

UNIT

ADREFHI

A-to-D high -voltage reference source

3.0

VCCAD

ADREFLO

A-to-D low-voltage reference source

VSSAD

0.3

VAI

Analog input voltage

ADREFLO

ADREFHI

IAIC

Analog input clamp current(2)

- 2

(VAI < VSSAD - 0.3 or VAI > VCCAD + 0.3)

(1)

For VCCAD and VSSAD recommended operating conditions, see Section 4.2.

(2)

Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.

Table 5-23. MibADC Operating Characteristics Over Full Range of Recommended Operating

Conditions(1)

PARAMETER

DESCRIPTION/CONDITIONS

MIN

NOM

MAX

UNIT

Rmux

Analog input mux on-resistance

See Figure 5-21

125

1.5K

Rsamp

ADC sample switch on-resistance

See Figure 5-21

150

1.5K

Cmux

Input mux capacitance

See Figure 5-21

Csamp

ADC sample capacitance

See Figure 5-21

IAIL

Analog input leakage current

Input leakage per ADC input pin

-200

200

IADREFHI

ADREFHI input current

ADREFHI = 3.6 V, ADREFLO = VSSAD

Conversion range over which

ADREFHI - ADREFLO

3.6

specified accuracy is maintained

Difference between the actual step

EDNL

Differential non-linearity error

width and the ideal value (see

± 2

LSB

Figure 5-22).

Maximum deviation from the best

straight line through the MibADC.

EINL

Integral non-linearity error

MibADC transfer characteristics,

± 2

LSB

excluding the quantization error (see

Figure 5-23).

Maximum value of the difference

ETOT

Total error/Absolute accuracy

between an analog value and the

± 2

LSB

ideal midstep value (see Figure 5-24).

(1)

1 - LSB = (ADREFHI – ADREFLO)/ 2

10 for the MibADC.

Peripheral Information and Electrical Specifications

Submit Documentation Feedback

Product Folder Link(s): TMS470MF06607

TMS470MF06607 Datasheet(PDF) 56 Page - Texas Instruments

TMS470MF06607 Datasheet(HTML) 56 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

Datasheet Download

Link URL