LM75A

www.ti.com

SNOS808P – JANUARY 2000 – REVISED DECEMBER 2014

6.6 Digital DC Characteristics

Unless otherwise noted, these specifications apply for +VS = 2.7 to 5.5 Vdc for LM75AIM and LM75AIMM. TA = TJ = 25°C,

unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX(2)

UNIT

–55°C

≤ TJ ≤ 125°C

+VS × 0.7

V

VIN(1)

Logical “1” Input Voltage

+VS + 0.3

V

–55°C

≤ TJ ≤ 125°C

−0.3

V

VIN(0)

Logical “0” Input Voltage

+VS × 0.3

V

VIN = +VS

0.005

IIN(1)

Logical “1” Input Current

μA

VIN = +VS, –55°C ≤

1.0

TJ ≤ 125°C

VIN = 0 V

−0.005

IIN(0)

Logical “0” Input Current

μA

VIN = 0 V, –55°C ≤

−1.0

TJ ≤ 125°C

CIN

All Digital Inputs

5

pF

High Level Output

VOH = 5 V, –55°C ≤

IOH

Current

LM75A

1

μA

TJ ≤ 125°C

Open drain leakage

IOL = 3 mA, –55°C ≤

0.4

VOL

Low Level Output Voltage

V

TJ ≤ 125°C

CL = 400 pF IO = 3

250

tOF

Output Fall Time

mA, –55°C

≤ TJ ≤

ns

125°C

(1)

Typicals are at TA = 25°C and represent most likely parametric norm.

(2)

Maximum values (limits) are ensured to AOQL (Average Outgoing Quality Level).

6.7 I

2C Digital Switching Characteristics

Unless otherwise noted, these specifications apply for +VS = 2.7 to 5.5 Vdc for LM75AIM and LM75AIMM on output lines = 80

pF unless otherwise specified. TA = TJ = 25°C, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX(2)(3)

UNIT

t1

SCL (Clock) Period

–55°C

≤ TJ ≤ 125°C

2.5

ns

t2

Data in Set-Up Time to SCL High

–55°C

≤ TJ ≤ 125°C

100

ns

t3

Data Out Stable after SCL Low

–55°C

≤ TJ ≤ 125°C

0

ns

t4

SDA Low Set-Up Time to SCL Low (Start

–55°C

≤ TJ ≤ 125°C

100

ns

Condition)

t5

SDA High Hold Time after SCL High (Stop

–55°C

≤ TJ ≤ 125°C

100

ns

Condition)

75

SDA Time Low for Reset of Serial

tTIMEOUT

LM75A

ms

Interface(4)

–55°C

≤ TJ ≤ 125°C

325

(1)

Typicals are at TA = 25°C and represent most likely parametric norm.

(2)

Maximum values (limits) are ensured to AOQL (Average Outgoing Quality Level).

(3)

Timing specifications are tested at the bus input logic levels (Vin(0)=0.3XVA for a falling edge and Vin(1)=0.7XVA for a rising edge)

when the SCL and SDA edge rates are similar.

(4)

Holding the SDA line low for a time greater than tTIMEOUT will cause the LM75A to reset SDA to the IDLE state of the serial bus

communication (SDA set High).

Copyright © 2000–2014, Texas Instruments Incorporated

Submit Documentation Feedback

5

Product Folder Links: LM75A