LM3550SPXSLASHNOPB datasheet(24/43 Pages) TI2

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ADR6

bit7

ADR5

bit6

ADR4

bit5

ADR3

bit4

ADR2

bit3

ADR1

bit2

ADR0

bit1

R/W

bit0

MSB

LSB

C Slave Address (chip address)

start

msb Chip Address lsb

ack

msb Register Add lsb

ack

msb

DATA

lsb

ack

stop

ack from slave

SCL

start

Id = 53h

ack

addr = 10h

ack

data = 08h

stop

SDA

LM3550

SNVS569C – MAY 2009 – REVISED OCTOBER 2016

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Programming (continued)

7.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge-related clock pulse is generated

by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LM3550 pulls

down the SDA line during the 9th clock pulse, signifying an acknowledge. The LM3550 generates an

acknowledge after each byte has been received.

After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W). The LM3550 address is 53h. For the eighth bit, a 0 indicates a

WRITE and a 1 indicates a READ. The second byte selects the register to which the data will be written. The

third byte contains data to write to the selected register.

w = write (SDA = 0)

ack = acknowledge (SDA pulled down by the slave)

id = chip address, 53h for LM3550

Figure 46. Write Cycle

7.5.1.4 I2C-Compatible Child Address: 0x53

LM3550SPX/NOPB Datasheet(PDF) 24 Page - Texas Instruments

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