LMH0318RTWR datasheet(21/59 Pages) TI2

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tSSSU

tSU

tPH

tPL

tSSH

tSSOF

SS_N

SCK

MOSI

MISO

A7'

A6'

A5'

A4'

A3'

A2'

A1'

D7'

D6'

D5'

D4'

D3'

D2'

D1'

D0'

A0'

R/W'

HiZ

todz

LMH0318

www.ti.com

SNLS508 – SEPTEMBER 2015

8.3.7.7 SPI Mode

The SPI (Serial Peripheral Interface) bus standard can be used to control the device. The SPI Mode is enabled

when MODE_SEL Pin 1 is pulled high through the 1-k

Ω resistor. The SPI bus comprises of 4 pins: Pin 2, Pin 3,

Pin 4, and Pin 15:

1. MOSI Pin 4: Master Output Slave Input. Configured as toggling input.

2. MISO Pin 15: Master Input, Slave Output: Configured as a toggling output

3. SS_N Pin 2: Slave Select (active low). Configured as toggling input.

4. SCK Pin 3: Serial clock (output from master). Configured as toggling input.

The maximum operating speed supported on the SPI bus is 20 MHz.

8.3.7.7.1

SPI READ/WRITE Transaction

Each SPI transaction to a single device is 17 bits long and is framed by SS_N asserted low. The MOSI input is

ignored and the MISO output is floated whenever SS_N is de-asserted (High).

The bits are shifted in left-to-right. The first bit is R/W, so it is 1 for reads and 0 for writes. Bits A7-A0 are the 8-bit

shifted out on MISO as the current command, address, and data are shifted in on MOSI. In all SPI transactions,

the MISO output signal is enabled asynchronously when SS_N becomes asserted.

R/W

Figure 8. MOSI Format

8.3.7.7.2

SPI Write Transaction Format

For SPI writes, the R/W bit is 0. SPI write transactions are 17 bits per device, and the command is executed on

the rising edge of SS_N, as shown in Figure 9. The SPI transaction always starts on the rising edge of the clock.

Figure 9. MOSI Write Sequence

The signal timing for a SPI Write transaction is shown in Figure 10. The “prime” values on MISO (for example,

‟) reflect the contents of the shift register from the previous SPI transaction, and are a "don’t-care" for the

current transaction.

Figure 10. Signal Timing for a SPI Write Transaction

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