LMH0318RTWR datasheet(8/59 Pages) TI2

8 / 59 page

LMH0318

SNLS508 – SEPTEMBER 2015

www.ti.com

Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

3.3-V TOLERANT LVCMOS / LVTTL DC SPECIFICATIONS (SDA, SCL, LOS_INT_N)

VIH25

High level input voltage

2.5 V Supply Voltage

1.75

3.6

VIL

Low level input voltage

GND

0.8

VOL

Low level output voltage

IOL = 1.25 mA

0.4

IIH

Input high current

VIN = 2.5 V, VDD = 2.5 V

μA

IIL

Input low current

VIN = GND, VDD = 2.5 V

-10

μA

SIGNAL DETECT

SDH

Signal detect (default)

2.97 Gbps, EQ

mVP-P

Assert threshold level(1)(2)

Pathological Pattern

2.97 Gbps, PLL

mVP-P

Pathological Pattern

2.97 Gbps, PRBS10

mVP-P

Pattern

SDL

Signal detect (default)

2.97 Gbps EQ

mVP-P

De-assert threshold

Pathological Pattern

level(1)

2.97 Gbps, PLL

mVP-P

Pathological Pattern

2.97 Gbps, PRBS10

mVP-P

Pattern

HIGH SPEED RECEIVE RX INPUTS (IN_n+, IN_n-)

R_RD

DC Input differential

100

125

Ω

resistance

RLRX-SDD

Input differential return

Measured with the device

loss(3)(4)

powered up.

-14

SDD11 10 MHz to 2 GHz

SDD11 2 GHz to 3 GHz

-6.5

RLRX-SCD

Differential to common

Measure with the device

mode Input

powered up.SCD11, 10

-20

conversion(3)(4)

MHz to 3 GHz

HIGH SPEED OUTPUTS (OUT_n+, OUT_n-)

VVOD_OUT1

Output differential

Default setting, 8T clock

400

600

700

mVP-P

voltage(3)(4)

pattern

VVOD_OUT1_DE

De-emphasis Level

VOD = 600mV, maximum

De-Emphasis with 16T

-9

clock pattern

VVOD_OUT1_CLK

Clock output differential

2.97 GHz,1.485 GHz, and

560

mVP-P

voltage

270 MHz

VVOD_OUT0

Output single ended

Default setting

voltage at OUT0+ with

720

800

880

mVP-P

OUT0- terminated(5)(3)

RDIFF_OUT1

DC output differential

100

Ω

resistance

(1)

Data with extraordinarily long periods of high-frequency 1010 data, and for long, lossy channels, the signal amplitude at the input to the

device may be severely attenuated by the channel and may fall below the signal detect assert and/or de-assert thresholds.

(2)

The voltage noise on the receiver inputs which has an amplitude larger than the signal detect assert threshold may trigger a signal

detect assert condition

(3)

These limits are ensured by bench characterization and are not production tested.

(4)

Dependent on board layout. Characterization data was measured with LMH1218EVM evaluation board

(5)

ATE Production tested using DC method. Apply differential DC signal at the input and measure OUT0P amplitude. OUT0N terminated in

75 Ohm.

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