LMH0318RTWR datasheet(40/59 Pages) TI2

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LMH0318

SNLS508 – SEPTEMBER 2015

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8.5.5 Transmitter Registers

Table 8. Transmitter Registers

FIELD REGISTER

BITS

DEFAULT

R/RW

DESCRIPTION

ADDRESS

Out0_Mux_Select

Reg 0x1C Channel

0x18

OUT0 Mux Selection

pfd_sel0_data_mux[2]

When 0x09[5] = 1'b OUT0 Mux

Selection can be controlled as follows:

pfd_sel0_data_mux[1]

000: Mute

pfd_sel0_data_mux[0]

001: 10 MHz Clock

010: Raw Data

100: Retimed Data

Other Settings - Invalid

vco_clk_sel

When 0x09[5] = 1'b and 0x1E[[7:5] =

101'b OUT1 clock selection can be

controlled as follows:

1: OUT1 puts out line rate clock

0: OUT1 puts out 10MHz clock

mr_drv_out_ctrl[1]

Controls both OUT0 and OUT1:

00:

mr_drv_out_ctrl[0]

OUT0: Mute

OUT1: Mute

01:

OUT0: Locked Reclocked Data /

Unlocked Raw Data

OUT1: Locked Output Clock / Unlocked

Mute

10:

OUT0: Locked Reclocked Data /

Unlocked RAW

OUT1: Locked Reclocked Data /

Unlocked Raw

11:

OUT0: Forced Raw

OUT1: Forced Raw

Reserved

OUT1_Mux_Select

Reg 0x1E Channel

0xE9

OUT1 Mux Selection

pfd_sel_data_mux[2]

When 0x09[5] = 1'b OUT0 Mux

Selection can be controlled as follows:

pfd_sel_data_mux[1]

111: Mute

pfd_sel_data_mux[0]

101: 10MHz Clock if reg 0x1c[4]=0 and

full rate clock if reg 0x1c[4] = 1

010: Full Rate Clock

001: Retimed Data

000: Raw Data

Other Settings - Invalid

Reserved

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