CLK

DIN

CS_N

I...

I12

I13

I16

I14

I15

TD

DOUT

MODE

T-1

T0

T1

T12

T13

T14

T15

T16

TS

TH

0

1

0

1

I0

I1

1

0

1

0

1

0

CFG

1

0

I1

I0

TS

TS

LMH6580, LMH6581

www.ti.com

SNOSAY4C – AUGUST 2007 – REVISED MAY 2013

Figure 66. Timing Diagram for Serial Mode

Table 2. Serial Mode Data Frame (First Two Words)(1)

Output 0

Output 1

Input Address

On = 0

Input Address

On = 0

LSB

MSB

Off = 1

LSB

LSB

Off = 1

0

1

2

3

4

5

6

7

(1)

Off = TRI-STATE, Bit 0 is first bit clocked into device.

Table 3. Serial Mode Data Frame (Continued)

Output 2

Output 3

Input Address

On = 0

Input Address

On = 0

LSB

MSB

Off = 1

LSB

MSB

Off = 1

8

9

10

11

12

13

14

15

ADDRESSED PROGRAMMING MODE

Addressed programming mode makes it possible to change only one output register at a time. To utilize this

mode the mode pin must be High. All other pins function the same as in serial programming mode except that

the word clocked in is 5 bits and is directed only at the output specified. In addressed mode the data format is

shown below in Table 4.

Also illustrated is the timing relationships for the digital pins in Figure 67. It is important to note that all the pin

timing relationships are important, not just the data and clock pins. One example is that the Chip Select pin (CS)

must transition low before the first rising edge of the clock signal. This allows the internal timing circuits to

synchronize to allow data to be accepted on the next falling edge. The chip select pin must then transition high

after the final data bit has been clocked in and before another clock signal positive edge occurs to prevent invalid

data from being clocked into the chip. Also, in addressed mode is it necessary for the clock signal to make a low

to high transition after the chip select pin has been brought high. If there is not a low to high transition of the

clock after the chip select pin goes high subsequent data wil not be loaded into the chip properly. The configure

(CFG) pin timing is not critical, but it does need to be kept low until all data has been shifted into the crosspoint

registers.

Copyright © 2007–2013, Texas Instruments Incorporated

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