LP5562TMXSLASHNOPB datasheet(27/52 Pages) TI2

27 / 52 page

ADR6

Bit7

ADR5

bit6

ADR4

bit5

ADR3

bit4

ADR2

bit3

ADR1

bit2

ADR0

bit1

R/W

bit0

MSB

LSB

C SLAVE address (chip address)

SVA-30197413

LP5562

www.ti.com

SNVS820B – APRIL 2013 – REVISED DECEMBER 2016

Product Folder Links: LP5562

Submit Documentation Feedback

7.5.2.3 Acknowledge Cycle

The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte

transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter

releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver

must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the

high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to

receive the next byte.

7.5.2.4 Acknowledge After Every Byte Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge

signal after every byte received.

There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked

out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the

master), but the SDA line is not pulled down.

7.5.2.5 Addressing Transfer Formats

Each device on the bus has a unique slave address. The LP5562 operates as a slave device with the 7-bit

address. LP5562 I2C address is pin selectable from four different choices. If 8-bit address is used for

programming, the 8th bit is 1 for read and 0 for write. Table 24 shows the 8-bit I2C addresses.

Table 24. I2C Addresses

ADDR_SEL

[1:0]

I 2 C ADDRESS WRITE

(8 bits)

I 2 C ADDRESS READ

(8 bits)

0110 0000 = 60h

0110 0001 = 61h

0110 0010 = 62h

0110 0011 = 63h

0110 0100 = 64h

0110 0101 = 65h

0110 0110 = 66h

0110 0111 = 67h

Before any data is transmitted, the master transmits the address of the slave being addressed.

The slave device should send an acknowledge signal on the SDA line, once it recognizes its address.

The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends

on the bit sent after the slave address — the eighth bit.

When the slave address is sent, each device in the system compares this slave address with its own. If there is a

match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the

R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.

Figure 23. I2C chip address

7.5.2.6 Control Register Write Cycle

•

Master device generates start condition.

•

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

•

Slave device sends acknowledge signal if the slave address is correct.

•

Master sends control register address (8 bits).

•

Slave sends acknowledge signal.

•

Master sends data byte to be written to the addressed register.

LP5562TMX/NOPB Datasheet(PDF) 27 Page - Texas Instruments

LP5562TMX/NOPB Datasheet(HTML) 27 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL