SLAS787 datasheet(12/52 Pages) TI2

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MSP430G2231-Q1

SLAS787B – NOVEMBER 2011 – REVISED MARCH 2014

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8.8 Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all

instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).

8.8.1 Oscillator and System Clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal

oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO).

The basic clock module is designed to meet the requirements of both low system cost and low power

consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1µs. The basic

clock module provides the following clock signals:

•

Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.

•

Main clock (MCLK), the system clock used by the CPU.

•

Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

Table 9. DCO Calibration Data (Provided From Factory In Flash Information

Memory Segment A)

CALIBRATION

DCO FREQUENCY

SIZE

ADDRESS

CALBC1_1MHZ

byte

010FFh

1 MHz

CALDCO_1MHZ

byte

010FEh

8.8.2 Brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and

power off.

8.8.3 Digital I/O

There is one 8-bit I/O port implemented—port P1—and two bits of I/O port P2:

•

All individual I/O bits are independently programmable.

•

Any combination of input, output, and interrupt condition is possible.

•

Edge-selectable interrupt input capability for all the eight bits of port P1 and the two bits of port P2.

•

Read/write access to port-control registers is supported by all instructions.

•

Each I/O has an individually programmable pull-up/pull-down resistor.

8.8.4 WDT+ Watchdog Timer

The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be disabled or configured as an interval timer and can

generate interrupts at selected time intervals.

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