ISL81801EVAL2Z datasheet(38/50 Pages) RENESAS

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ISL81801

5. Functional Description

FN8937 Rev.1.4

Page 38 of 49

Mar 8, 2024

circuit. The buffer output is connected to the iSh bus using R28 in Converter 1 and R61 in Converter 2 to create the

reference signal. The voltage on the iSh bus, ViSh, is calculated using Equation 16.

where VIMON_OUT1 is the Converter 1 IMON_OUT pin voltage and VIMON_OUT2 is the Converter 2 IMON_OUT pin

voltage.

The second op amp, U2A in Converter 1 or U4A in Converter 2 is a differential op amp to feed the current error

signal to the IC FB_OUT pin. The differential input signal is equal to VIMON_OUT1 - ViSh for U2A and

VIMON_OUT2 -ViSh for U4A. The differential op amp gain and the value of the resistor between the op amp output

and the FB_OUT pin is defined based on the current sharing accuracy and the allowed maximum output voltage

change caused by the current sharing loop, assuming the current sense circuit tolerance is ignored.

The maximum allowed current sharing error is represented by the maximum allowed differential op amp input.

The differential op amp outputs a maximum voltage of 5V at its maximum differential input, assuming a rail-to-rail

op amp is used. The differential op amp gain Ksh is calculated using Equation 17.

where ΔVsh is the maximum allowed differential op amp input voltage, which is proportional to the output current

sharing error ΔIsh = |IOUT1 – IOUT2| / 2. IOUT1 and IOUT2 are the output currents of Converter 1 and 2, respectively.

ΔVsh = ΔIsh x RIM_OUT x RS_OUT x GmISEN, referring to the descriptions in Input and Output Average Current

Monitoring and Regulation Loops.

As shown in Figure 54, Ksh = R23/R27 for Converter 1 and Ksh = R56/R58 for Converter 2.

The value Rsh of the resistor between the differential op amp output and the FB_OUT pin is calculated using

Equation 18.

where ΔVOUT is the maximum allowed output voltage change caused by the current sharing loop, which is limited

by the VOUT regulation tolerance.

RFBO1 is the resistance of the upper resistor of the VOUT voltage sense divider shown in Figure 43. As shown in

Figure 54, Rsh = R29 + R30 for Converter 1 and Rsh = R64 + R65 for Converter 2. RFBO1 = R18 for Converter 1 and

RFBO1 = R50 for Converter 2.

5.13 Gate Drivers

The ISL81801 integrates two almost identical high voltage driver pairs to drive both buck and boost MOSFET

pairs. Each driver pair consists of a gate control logic circuit, a low-side driver, a level shifter, and a high-side

driver.

The ISL81801 incorporates an adaptive dead time algorithm that optimizes operation with varying MOSFET

conditions. This algorithm provides approximately 16ns dead time between the switching of the upper and lower

MOSFETs. This dead time is adaptive and allows operation with different MOSFETs without having to externally

adjust the dead time using a resistor or capacitor. During turn-off of the lower MOSFET, the LGATE voltage is

monitored until it reaches a threshold of 1V, at which time the UGATE is released to rise. Adaptive dead time

circuitry monitors the upper MOSFET gate voltage during UGATE turn-off. When the upper MOSFET

gate-to-source voltage drops below a threshold of 1V, the LGATE is allowed to rise. Renesas recommends

against using a resistor between the driver outputs and the respective MOSFET gates, because it can interfere

with the dead time circuitry.

The low-side gate driver is supplied from VDD and provides a 3A peak sink and 2A peak source current. The

high-side gate driver can also deliver peak 3A sink and 2A source current. Gate-drive voltage for the upper

(EQ. 16)

ViSh

VIMON_OUT1 VIMON_OUT2

 2



(EQ. 17)

Ksh

Vsh



--------------

(EQ. 18)

Rsh

5RFBO1



VOUT



-----------------------------

ISL81801EVAL2Z Datasheet(PDF) 38 Page - Renesas Technology Corp

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