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STM32L151VD Datasheet(PDF) 119 Page - STMicroelectronics

Part # STM32L151VD
Description  Ultra-low-power 32-bit MCU ARM® Cortex®-M3, 384KB Flash, 48KB SRAM, 12KB EEPROM, LCD, USB, ADC, DAC, memory I/F
PDF  154 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L151VD Datasheet(HTML) 119 Page - STMicroelectronics

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DocID022027 Rev 11
119/154
STM32L151xD STM32L152xD
Electrical characteristics
129
tS(5)
Sampling time
Direct channels
2.4 V
≤VDDA ≤3.6 V
0.25
-
-
µs
Multiplexed channels
2.4 V
≤VDDA ≤3.6 V
0.56
-
-
Direct channels
1.8 V
≤VDDA ≤2.4 V
0.56
-
-
Multiplexed channels
1.8 V
≤VDDA ≤2.4 V
1-
-
-4
-
384
1/fADC
tCONV
Total conversion time
(including sampling time)
fADC = 16 MHz
1
-
24.75
µs
-
4 to 384 (sampling phase) +12
(successive approximation)
1/fADC
CADC
Internal sample and hold
capacitor
Direct channels
-
16
-
pF
Multiplexed channels
-
-
fTRIG
External trigger frequency
Regular sequencer
12-bit conversions
-
-
Tconv+1 1/fADC
6/8/10-bit conversions
-
-
Tconv
1/fADC
fTRIG
External trigger frequency
Injected sequencer
12-bit conversions
-
-
Tconv+2 1/fADC
6/8/10-bit conversions
-
-
Tconv+1 1/fADC
RAIN(6) Signal source impedance
-
-
50
k
Ω
tlat
Injection trigger conversion
latency
fADC = 16 MHz
219
-
281
ns
-3.5
-
4.5
1/fADC
tlatr
Regular trigger conversion
latency
fADC = 16 MHz
156
-
219
ns
-2.5
-
3.5
1/fADC
tSTAB
Power-up time
-
-
-
3.5
µs
1. The Vref+ input can be grounded if neither the ADC nor the DAC are used (this allows to shut down an external voltage
reference).
2. The current consumption through VREF is composed of two parameters:
- one constant (max 300 µA)
- one variable (max 400 µA), only during sampling time + 2 first conversion pulses
So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at
1Msps
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 4: Pin descriptions for further details.
4. VSSA or VREF- must be tied to ground.
5. Minimum sampling time is reached for an external input impedance limited to a value as defined in Table 66: Maximum
source impedance RAIN max.
6. External impedance has another high value limitation when using short sampling time as defined in Table 66: Maximum
source impedance RAIN max.
Table 64. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit



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