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STM32L151VD Datasheet(PDF) 26 Page - STMicroelectronics

Part # STM32L151VD
Description  Ultra-low-power 32-bit MCU ARM® Cortex®-M3, 384KB Flash, 48KB SRAM, 12KB EEPROM, LCD, USB, ADC, DAC, memory I/F
PDF  154 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L151VD Datasheet(HTML) 26 Page - STMicroelectronics

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Functional overview
STM32L151xD STM32L152xD
26/154
DocID022027 Rev 11
3.7
Memories
The STM32L151xD and STM32L152xD devices have the following features:
•
48 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
•
The non-volatile memory is divided into three arrays:
–
384 Kbytes of embedded Flash program memory
–
12 Kbytes of data EEPROM
–
Options bytes
Flash program and data EEPROM are divided into two banks, this enables writing in
one bank while running code or reading data in the other bank.
The options bytes are used to write-protect or read-out protect the memory (with 4
Kbytes granularity) and/or readout-protect the whole memory with the following
options:
–
Level 0: no readout protection
–
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
–
Level 2: chip readout protection, debug features (ARM Cortex-M3 JTAG and serial
wire) and boot in RAM selection disabled (JTAG fuse)
The whole non-volatile memory embeds the error correction code (ECC) feature.
3.8
FSMC (flexible static memory controller)
The FSMC supports the following modes: SRAM, PSRAM, NOR/OneNAND Flash.
Functionality overview:
•
Up to 26 bit address bus
•
Up to 16-bit data bus
•
Write FIFO
•
Burst mode
•
Code execution from external memory
•
Four chip select signals
•
Up to 32 MHz external access
3.9
DMA (direct memory access)
The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.



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