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SPC560D30X Datasheet(PDF) 64 Page - STMicroelectronics

Part # SPC560D30X
Description  32-bit MCU family built on the Power Architecture for automotive body electronics applications
PDF  82 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPC560D30X Datasheet(HTML) 64 Page - STMicroelectronics

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Electrical characteristics
SPC560D30x, SPC560D40x
64/82
DS6494 Rev 8
Note:
Operating conditions: TA = 25 °C, fperiph = 8 MHz to 48 MHz
4.18.2
DSPI characteristics
IDD_HV_ADC(ADC) CC T
ADC supply current
on VDD_HV_ADC
VDD = 5.5 V
Analog static consumption
(no conversion)
2×fperiph
µA
Analog dynamic
consumption (continuous
conversion)
75 × fperiph + 32 µA
IDD_HV(FLASH)
CC T
CFlash + DFlash
supply current on
VDD_HV
VDD = 5.5 V
8.21
mA
IDD_HV(PLL)
CC T
PLL supply current
on VDD_HV
VDD = 5.5 V
30 × fperiph
µA
1. fperiph is an absolute value.
2. During the conversion, the total current consumption is given from the sum of the static and dynamic consumption, i.e.,
(41 + 5) × fperiph.
Table 43. On-chip peripherals current consumption (continued)
Symbol
C
Parameter
Conditions
Typical value(1) Unit
Table 44. DSPI characteristics
No.
Symbol
C
Parameter
DSPI0/DSPI1
Unit
Min
Typ
Max
1tSCK
SR
D
SCK cycle time
Master mode
(MTFE = 0)
125
ns
D
Slave mode
(MTFE = 0)
125
D
Master mode
(MTFE = 1)
83
D
Slave mode
(MTFE = 1)
83
—fDSPI
SR D DSPI digital controller frequency
fCPU
MHz
tCSC
CC D
Internal delay between pad
associated to SCK and pad
associated to CSn in master
mode
Master mode
130(1)
ns
tASC
CC D
Internal delay between pad
associated to SCK and pad
associated to CSn in master
mode for CSn1
1
Master mode
130(1)
ns
2tCSCext(2) SR D CS to SCK delay
Slave mode
32
ns
3tASCext(3) SR D After SCK delay
Slave mode
1/fDSPI + 5
ns
4tSDC
CC D
SCK duty cycle
Master mode
tSCK/2
ns
SR D
Slave mode
tSCK/2



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