ICS8534AY-01LF datasheet(10/20 Pages) IDT

10 / 20 page

ICS8534-01

LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER

IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER

ICS8534AY-01 REV. A DECEMBER 6, 2007

Differential Clock Input Interface

The CLK /nCLK accepts LVPECL, LVDS, LVHSTL and other

differential signals. Both VSWING and VOH must meet the VPP and

VCMR input requirements. Figures 3A to 3F show interface

examples for the HiPerClockS CLK/nCLK input driven by the most

common driver types. The input interfaces suggested here are

examples only. If the driver is from another vendor, use their

termination recommendation. Please consult with the vendor of the

driver component to confirm the driver termination requirements.

Figure 3A. HiPerClockS CLK/nCLK Input Driven by an

IDT Open Collector CML Driver

Figure 3C. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 3E. HiPerClockS CLK/nCLK Input

Driven by an SSTL Driver

Figure 3B. HiPerClockS CLK/nCLK Input

Driven by a Built-In Pullup CML Driver

Figure 3D. HiPerClockS CLK/nCLK Input Driven by

a 3.3V LVPECL Driver with AC Couple

Figure 3F. HiPerClockS CLK/nCLK Input Driven by

a 3.3V LVDS Driver

CLK

nCLK

HiPerClockS

CML

3.3V

Zo = 50

Ω

Zo = 50

Ω

3.3V

125

3.3V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

LVPECL

HiPerClockS

CLK

nCLK

HiPerClockS

SSTL

2.5V

Zo = 60

Ω

Zo = 60

Ω

2.5V

3.3V

120

3.3V

100

CML Built-In Pullup

CLK

nCLK

3.3V

HiPerClockS

Zo = 50

Ω

Zo = 50

Ω

125

100 - 200

CLK

nCLK

3.3V LVPECL

3.3V

Zo = 50

Ω

Zo = 50

Ω

3.3V

HiPerClockS

3.3V

100

LVDS

CLK

nCLK

3.3V

HiPerClockS

Zo = 50

Ω

Zo = 50

Ω

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