Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

A/D CONVERTER TIMINGS

Conv. start set up time

200

ns

Conv. Start hold time

200

ns

Falling edge of clock to data

out valid delay

≤ 20pF

200

ns

ConvStart falling edge to output

in Hi-Z delay

200

ns

Clock frequency

250

KHz

Conv. Start low level time

5.6

µs

Theoretical acquisition time

32.4

µs

Real acquisition time

36

µs

DIGITAL INTERFACE INPUT

Schmitt Trigger positive-going

Threshold

V

Schmitt Trigger negative-going

Threshold

V

Scmitt Trigger Hysteresis

0.1

0.3

1

V

Input Current (Vin=0; Vdd=5)*

50

150

300

µA

* This applies to input pins having an internal pull-up (ENABLE_CHANNEL, LONG_PULSE, SHORT_PULSE)

CR LATCH TIMINGS

Latch set up time

100

ns

Latch high time

100

ns

Latch data valid to A/D input

valid delay

Selected channel:

CH1..CH5

CH0

4

7

µs

µs

NB: The control register (driving signals CRdata, CRclock) is accessed with the same timing specifications as the

data 16 bit shift register (signals Serial data, Serial clock)

SHIFT REGISTER AND LATCH TIMING

Set up time

50

ns

Hold time

50

ns

Serial clock low time

50

ns

Serial clock high time

50

ns

Serial clock period

150

ns

Latch set up time

100

ns

Latch data high time

100

ns

Long Pulse set_up time with

respect to NCEn

160

ns

Long Pulse hold time with

respect to NCEn

0ns

OUTPUTS ELECTRICAL CHARACTERISTICS

Output Current (outputs 0..15)

DC=33%;

preheating DC=66%

400

mA

On Resistance

°C

1.3

Ω

Turn on Time (Tdelay + Trise)

From 50% Long Pulse to 90%

power output rising edge

Load = 30 Ohm in parallel with

1.5nF

160

ns

Toff delay time

From 50% Long Pulse to 90%

power output falling edge

Load = 30 Ohm in parallel with

1.5nF

100

ns

°C)

L6452

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