Pin #

Name

Function

30

NCEn

A high level enables the internal current sources and disables all DMOS outputs. To

be active, the internal current sources must have their corrsponding bit set in the 16 bit

latch and Long Pulse must be set to low level. A low level enables the internal HSA/B

short circuit detection

31

Latch Data

A rising edge latches the 16 bit stored in the shift register in the 16 bit latch

32

SDI

Serial data input of the shift register

33

SDC

The data bit presented to the Serial Data Input pin is stored into the register on the

rising edge of this pin

34

Long Pulse

A low level activates all outputs having their coresponding bit in the 16 bit latch set

(this pin has an internal pull-up resistor)

35

Short Pulse

A low level activates all outputs having their coresponding bit in the 16 bit latch reset

(this pin has an internal pull-up resistor)

36

_Reset

A low level disables all functions and clears all registers

37

ConvStart

A high level enables the A/D to start the new conversion

38

ADCK

A/D clock signal; the ADDATA signal are valid on the falling edge of this pin

39

NCOut

If Nozzle Check Enable is high this output provides a high level when the open load is

detected on the output. If Nozzle Check Enable is low this output provides a high level

when a short circuit is detected on HSA/B output

40

CH0_buf

Analog output signal (CH0 buffered)

41

ADDATA

A/D serial data output

42

AnalogGND

Analog ground connection

43

ADCGND

Ground of internal ADC

44, 90

Va

Power supply

45

Vref

Reference voltage generator

46 to 50

CH5..CH1

A/D input signals

52 to 64

HSB1..HSB13

Head selector address output channel B

65

Vr

Head Select Power Supply

66 to 78

HSA13..HSA1

Head selector address output channel A

80

EnlC

A high level enables the counter and the internal decoder will activate of the HSx

outputs according to the counter’s outputs. Signal S0 becomes Clock Counter and S1

becomes Reset Counter

81

ChSel

A low level enables channel A and a high level enables channel B

82

S3

Decoder input signals when Enable Counter is low

83

UpC/ S2

A high level enables the internal counter to up counting. A low level enables down

counting

84

ResC/S1

A low level resets the internal counter

85

_EnCh

A low level enables the selected channel (this input has an internal pull up resistor)

86

ClkC/S0

A high level clocks the internal counter

87

Step up GND

Ground of step up block

88

Step up boost

Boost voltage

89

Vstep up

Driving voltage of power DMOS stage

91

VDD

5V logic supply

93

Rext

An external resistor connected versus ground fixes the internal current source value

94, 95

RxB, RxA

Current source outputs

96, 97

VxA, VxB

RxA, RxB voltage after an optional external filter

98

_ONenable

A low level enables the current source generator according the _A/B and ON/_OFF

control register bit

99

CRclock

Data on pin CRdata are stored into the register on the rising edge of this pin

100

CRdata

Control register serial data input

PIN FUNCTIONS (continued)

L6452

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