AM79C961KCSLASHW datasheet(95/173 Pages) AMD

95 / 173 page

P R E L I M I N A R Y

AMD

1-569

Am79C961

ISACSR7: LED3 Status

Bit

Name

Description

ISACSR7

controls

the

func-

tion(s)

that

the

LED3

displays. Multiple functions can

be simultaneously enabled on

this LED pin. The LED display will

indicate the logical OR of the

enabled functions. ISACSR7 de-

faults to Transmit Status (XMT)

with pulse stretcher enabled

(PSE = 1) and is fully program-

mable.

LEDOUT

Indicates

the

current

(non-

stretched) state of the function(s)

generated. Read only.

14-8

RES

Reserved locations. Read and

written as zero.

PSE

Pulse Stretcher Enable. Extends

the LED illumination for each en-

abled function occurrence.

0 is disabled, 1 is enabled.

RES

Reserved locations. Read and

written as zero.

RCVADDM

Receive Address Match. This bit

when set allows for LED control

of only receive packets that

match internal address match.

XMT E

Enable Transmit Status Signal.

Indicates PCnet-ISA+ controller

transmit activity .

0 disables the signal, 1 enables

the signal.

Enable Receive Polarity Signal.

RVPOL E

Enables LED pin assertion when

receive polarity is correct on the

10BASE-T port. Clearing the bit

indicates this function is to be

ignored.

RCV E

Enable Receive Status Signal.

Indicates receive activity on the

network.

0 disables the signal, 1 enables

the signal.

JAB E

Enable Jabber Signal. Indicates

the PCnet-ISA+ controller is jab-

bering on the network.

0 disables the signal, 1 enables

the signal.

COL E

Enable Collision Signal. Indi-

cates collision activity on the

network.

0 disables the signal, 1 enables

the signal.

ISACSR8: Software Configuration Register

(Read-Only Register)

Bit

Description

15–12

Read-only image of SR_AM(3:0) of P&P

11–8

Read-only image of BP_AM(3:0) of P&P

7–4

Read-only image of IRQSEL(3:0) of P&P

Reserved, written with zero,

read as undefined.

2–0

Read-only image of DMASEL(2:0) of

P&P register 0x74.

Initialization Block

The figure below shows the Initialization Block memory

configuration. Note that the Initialization Block must be

based on a word (16-bit) boundary.

Bits

Address

15–12

11–8

7–4

3–0

IADR+00

MODE 15-00

IADR+02

PADR 15-00

IADR+04

PADR 31-16

IADR+06

PADR 47-32

IADR+08

LADRF 15-00

IADR+10

LADRF 31-16

IADR+12

LADRF 47-32

IADR+14

LADRF 63-48

IADR+16

RDRA 15-00

IADR+18

RLEN

RES

RDRA 23-16

IADR+20

TDRA 15-00

IADR+22

TLEN

RES

TDRA 23-16

RLEN and TLEN

The TLEN and RLEN fields in the initialization block are

3 bits wide, occupying bits 15,14, and 13, and the value

in these fields determines the number of Transmit and

Receive Descriptor Ring Entries (DRE) which are used

in the descriptor rings. Their meaning is as follows:

AM79C961KC/W Datasheet(PDF) 95 Page - Advanced Micro Devices

AM79C961KC/W Datasheet(HTML) 95 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL