M36DR432AD datasheet(13/52 Pages) STMICROELECTRONICS

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M36DR432AD, M36DR432BD

Figure 5. Flash Security Block and Protection Register Memory Map

Flash Bus Operations

The following operations can be performed using

the appropriate bus cycles: Flash Read Array

(Random and Page Modes), Flash Write, Flash

Output Disable, Flash Standby and Flash Reset/

Power-Down, see Table

2, Main Operation

Modes.

Flash Read. Flash Read operations are used to

output the contents of the Memory Array, the Elec-

tronic Signature, the Status Register, the CFI, the

Block Protection Status or the Configuration Reg-

ister status. Read operation of the Flash memory

array is performed in asynchronous page mode,

that provides fast access time. Data is internally

read and stored in a page buffer. The page has a

size of 4 words and is addressed by A0-A1 ad-

dress inputs. Read operations of the Electronic

Signature, the Status Register, the CFI, the Block

Protection Status, the Configuration Register sta-

tus and the Security Code are performed as single

asynchronous read cycles (Random Read). Both

Flash Chip Enable EF and Flash Output Enable

GF must be at VIL in order to read the output of the

memory.

Flash Write. Write operations are used to give

commands to the memory or to latch Input Data to

be programmed. A write operation is initiated

when Chip Enable EF and Write Enable WF are at

VIL with Output Enable GF at VIH. Addresses are

latched on the falling edge of WF or EF whichever

occurs last. Commands and Input Data are

latched on the rising edge of WF or EF whichever

occurs first. Noise pulses of less than 5ns typical

on EF, WF and GF signals do not start a write cy-

cle.

Flash Output Disable. The data outputs are high

impedance when the Output Enable GF is at VIH

with Write Enable WF at VIH.

Flash Standby. The memory is in standby when

Chip Enable EF is at VIH and the P/E.C. is idle.

The power consumption is reduced to the standby

level and the outputs are high impedance, inde-

pendent of the Output Enable GF or Write Enable

WF inputs.

Automatic Flash Standby. In Read mode, after

150ns of bus inactivity and when CMOS levels are

driving the addresses, the chip automatically en-

ters a pseudo-standby mode where consumption

is reduced to the CMOS standby value, while out-

puts still drive the bus.

Flash Power-Down. The memory is in Power-

Down when the Configuration Register is set for/

Power-Down and RPF is at VIL. The power con-

sumption is reduced to the Power-Down level, and

Outputs are high impedance, independent of the

Chip Enable EF, Output Enable GF or Write En-

able WF inputs.

Dual Bank Operations. The Dual Bank allows

data to be read from one bank of memory while a

program or erase operation is in progress in the

other bank of the memory. Read and Write cycles

can be initiated for simultaneous operations in dif-

ferent banks without any delay. Status Register

during Program or Erase must be monitored using

an address within the bank being modified.

Flash Command Interface

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. An internal Program/Erase Controller han-

AI06185

Parameter Block # 0

User Programmable OTP

Unique device number

Protection Register Lock

88h

85h

84h

81h

80h

SECURITY BLOCK

PROTECTION REGISTER

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