M36DR432AD datasheet(42/52 Pages) STMICROELECTRONICS

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M36DR432AD, M36DR432BD

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Table 24. SRAM Write AC Characteristics

Note: 1. tAS is measured from the address valid to the beginning of write.

2. tWR is measured from the end or write to the address change. tWR applied in case a write ends as ES or WS goes High.

3. tCW is measured from ES going Low end of write.

4. A Write occurs during the overlap (tWP) of Low ES and Low WS. A write begins when ES goes Low and WS goes Low with asserting

UBS or LBS for single byte operation or simultaneously asserting UBS and LBS for double byte operation. A write ends at the ear-

liest transition when ES goes High and WS goes High. The tWP is measured from the beginning of write to the end of write.

Figure 24. SRAM Low VDDS Data Retention AC Waveforms, ES Controlled

Symbol

Alt

Parameter

SRAM

Unit

Min

Max

tAVAV

tWC

Write Cycle Time

tAVEL

tAS

(1)

Address Valid to Chip Enable Low

tAVWH

tAW

Address Valid to Write Enable High

tAVWL

tAS

(1)

Address Valid to Write Enable Low

tBLWH

tBW

UBS, LBS Valid to End of Write

tDVWH

tDW

Input Valid to Write Enable High

tEHAX

tWR

(2)

Chip Enable High to Address Transition

tELWH,

tCW

(3)

Chip Select to End of Write

tWHAX

tWR

(2)

Write Enable High to Address Transition

tWHDX

tDH

Write Enable High to Input Transition

tWHQX

tOW

Write Enable High to Output Transition

tWLQZ

tWHZ

Write Enable Low to Output Hi-Z

tWLWH

tWP

(4)

Write Enable Pulse Width

AI07325

1.65 V

tCDR

≥ VDDS – 0.2V

1.0 V

VDR ≥

VDDS

DATA RETENTION MODE

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