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M36DR432AD Datasheet(PDF) 49 Page - STMicroelectronics |
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M36DR432AD Datasheet(HTML) 49 Page - STMicroelectronics |
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49 / 52 page  49/52 M36DR432AD, M36DR432BD Table 34. CFI Query System Interface Information Offset Data Description 1Bh 0017h VDDF Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts 1Ch 0022h VDDF Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts 1Dh 0000h VPPF [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Note: This value must be 0000h if no VPPF pin is present 1Eh 00C0h VPPF [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Note: This value must be 0000h if no VPPF pin is present 1Fh 0004h Typical timeout per single byte/word program (multi-byte program count = 1), 2n µs (if supported; 0000h = not supported) 20h 0003h Typical timeout for maximum-size multi-byte program or page write, 2n µs (if supported; 0000h = not supported) 21h 000Ah Typical timeout per individual block erase, 2n ms (if supported; 0000h = not supported) 22h 0000h Typical timeout for full chip erase, 2n ms (if supported; 0000h = not supported) 23h 0003h Maximum timeout for byte/word program, 2n times typical (offset 1Fh) (0000h = not supported) 24h 0004h Maximum timeout for multi-byte program or page write, 2n times typical (offset 20h) (0000h = not supported) 25h 0002h Maximum timeout per individual block erase, 2n times typical (offset 21h) (0000h = not supported) 26h 0000h Maximum timeout for chip erase, 2n times typical (offset 22h) (0000h = not supported) |
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