21/52

M36DR432AD, M36DR432BD

Table 10. Flash Lock Status

Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read

2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WPF status.

Flash Status Register

The Status Register provides information on the

current or previous Program or Erase operations.

Bus Read operations from any address within the

bank, always read the Status Register during Pro-

gram and Erase operations.

The various bits convey information about the sta-

tus and any errors of the operation.

The bits in the Status Register are summarized in

Table 12, Status Register Bits. Refer to Tables 11

and 12 in conjunction with the following text de-

scriptions.

Data Polling Bit (DQ7). When Program opera-

tions are in progress, the Data Polling bit outputs

the complement of the bit being programmed on

DQ7. For a Double Word Program operation, it is

the complement of DQ7 for the last Word written to

the Command Interface.

During an Erase operation, it outputs a ’0’. After

completion of the operation, DQ7 will output the bit

last programmed or a ’1’ after erasing.

Data Polling is valid and only effective during P/

E.C. operation, that is after the fourth WF pulse for

programming or after the sixth WF pulse for erase.

It must be performed at the address being pro-

grammed or at an address within the block being

erased. See Figure 22 for the Data Polling flow-

chart and Figure 13 for the Data Polling wave-

forms.

DQ7 will also flag an Erase Suspend by switching

from ’0’ to ’1’ at the start of the Erase Suspend. In

order to monitor DQ7 in the Erase Suspend mode

an address within a block being erased must be

provided. DQ7 will output ’1’ if the read is attempt-

ed on a block being erased and the data value on

other blocks. During a program operation in Erase

Suspend, DQ7 will have the same behavior as in

the normal program.

Toggle Bit (DQ6). When Program or Erase oper-

ations are in progress, successive attempts to

read DQ6 will output complementary data. DQ6

will toggle following the toggling of either GF or EF.

The operation is completed when two successive

reads give the same output data. The next read

will output the bit last programmed or a ’1’ after

erasing.

The Toggle Bit DQ6 is valid only during P/E.C. op-

erations, that is after the fourth WF pulse for pro-

gramming or after the sixth WF pulse for Erase.

DQ6 will be set to ’1’ if a read operation is attempt-

ed on an Erase Suspend block. When erase is

suspended DQ6 will toggle during programming

operations in a block different from the block in

Erase Suspend.

See Figure 16 for Toggle Bit flowchart and Figure

14 for Toggle Bit waveforms.

Toggle Bit (DQ2). Toggle Bit DQ2, together with

DQ6, can be used to determine the device status

during erase operations.

During Erase Suspend a read from a block being

erased will cause DQ2 to toggle. A read from a

block not being erased will output data. DQ2 will

be set to '1' during program operation and to ‘0’ in

erase operation. If a read operation is addressed

to a block where an erase error has occurred, DQ2

will toggle.

Current

(WPF, DQ1, DQ0)

(WPF, DQ1, DQ0)

Current State

Program/Erase

Allowed

After

Block Lock

Command

After

Block Unlock

Command

After Block

Lock-Down

Command

After

WPF transition

1,0,0

yes

1,0,1

1,0,0

1,1,1

0,0,0

no

1,0,1

1,0,0

1,1,1

0,0,1

1,1,0

yes

1,1,1

1,1,0

1,1,1

0,1,1

1,1,1

no

1,1,1

1,1,0

1,1,1

0,1,1

0,0,0

yes

0,0,1

0,0,0

0,1,1

1,0,0

no

0,0,1

0,0,0

0,1,1

1,0,1

0,1,1

no

0,1,1

0,1,1

0,1,1