MSC8103 datasheet(47/104 Pages) FREESCALE

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AC Timings

MSC8103 Network Digital Signal Processor, Rev. 11

Freescale Semiconductor

2-7

2.6 AC Timings

The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and

inputs. AC timings are based on a 50 pF load, except where noted otherwise, and 50

Ω transmission line.

2.6.1

Output Buffer Impedances

2.6.2

Start-Up Timing

Starting the device requires coordination among several input sequences including clocking, reset, and power.

Section 2.6.3 describes the clocking characteristics. Section 2.6.4 describes the reset and power-up characteristics.

You must use the following guidelines when starting up an MSC8103 device:

•

PORESET

and TRST must be asserted externally for the duration of the power-up sequence. See Table 2-14

for timing.

•

If possible, bring up the VDD and VDDH levels together. For designs with separate power supplies, bring up

the VDDH levels and then the VDD levels (see Figure 2-5 and Figure 2-6).

•

CLKIN

can start toggling after VDDH reaches its nominal level, but it must toggle before VDD reaches 0.5 V to

guarantee correct device operation (see Figure 2-4 and Figure 2-6).

The following figures show acceptable start-up sequence examples. Figure 2-4 shows a sequence in which VDD and

VDDH are raised together. Figure 2-5 shows a sequence in which CLKIN starts toggling after VDDH reaches its

nominal level and before VDD is applied. Figure 2-6 shows a sequence in which VDD is raised after VDDH and CLKIN

begins to toggle shortly before VDD reaches the 0.5 V level.

Table 2-9.

Output Buffer Impedances

Output Buffers

Typical Impedance (

Ω)

System Bus

Memory Controller

Parallel I/O

Note:

These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.

Figure 2-4.

Start-Up Sequence with VDD and VDDH Raised Together

Time

o.5 V

3.3 V

1.6 V

VDDH Nominal Level

PORESET/TRST Asserted

VDD Nominal Level

CLKIN Starts Toggling

VDD/VDDH Applied

PORESET/TRST Deasserted

2.2 V

VDDH = Nominal Value

VDD = Nominal Value

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