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MSC8103 Datasheet(PDF) 62 Page - Freescale Semiconductor, Inc |
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MSC8103 Datasheet(HTML) 62 Page - Freescale Semiconductor, Inc |
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62 / 104 page ![]() MSC8103 Network Digital Signal Processor, Rev. 11 2-22 Freescale Semiconductor Physical and Electrical Specifications Figure 2-16 shows Host DMA read timing. Figure 2-17 shows Host DMA write timing. Figure 2-16. Host DMA Read Timing Diagram, HPCR[OAD] = 0 Figure 2-17. Host DMA Write Timing Diagram, HPCR[OAD] = 0 RX[0–3] Read Data Valid 64 44a 63 44b 51 50 49 52 (Output) HREQ HACK HD[0–15] (Output) TX[0–3] Write Data Valid 63 64 46 45 47 48 (Output) HREQ HACK HD[0–15] (Output) |
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