MSC8103 datasheet(20/104 Pages) FREESCALE

20 / 104 page

MSC8103 Network Digital Signal Processor, Rev. 11

1-16

Freescale Semiconductor

Signals/Connections

1.6.1

Port A Signals

Table 1-7.

Port A Signals

Name

Dedicated

I/O Data

Direction

Description

General-

Purpose I/O

Peripheral Controller:

Dedicated Signal

Protocol

PA31

FCC1: TXENB

UTOPIA master

FCC1: TXENB

UTOPIA slave

FCC1: COL

MII

Output

Input

FCC1: UTOPIA Master Transmit Enable

Asserted by the MSC8103 (UTOPIA master PHY) when there is valid

transmit cell data (TXD[0–7]).

FCC1: UTOPIA Slave Transmit Enable

Asserted by an external UTOPIA master PHY when there is valid

transmit cell data (TXD[0–7]).

FCC1: Media Independent Interface Collision Detect

Asserted by an external fast Ethernet PHY when collision is detected.

PA30

FCC1: TXCLAV

UTOPIA slave

FCC1: TXCLAV

UTOPIA master, or

FCC1: TXCLAV0

UTOPIA master, Multi-PHY, direct

polling

FCC1: RTS

HDLC, Serial and Nibble

FCC1: CRS

MII

Output

Input

Output

Input

FCC1: UTOPIA Slave Transmit Cell Available

Asserted by the MSC8103 (UTOPIA slave PHY) when the MSC8103

can accept one complete ATM cell.

FCC1: UTOPIA Master Transmit Cell Available

Asserted by an external UTOPIA slave PHY to indicate that it can accept

one complete ATM cell.

FCC1: UTOPIA Master Transmit Cell Available Multi-PHY Direct

Polling

Asserted by an external UTOPIA slave PHY using direct polling to

indicate that it can accept one complete ATM cell.

FCC1: Request To Send

In the standard modem interface signals supported by FCC1 (RTS,

CTS, and CD). RTS is asynchronous with the data. RTS is typically used

in conjunction with CD. The MSC8103 FCC1 transmitter requests the

receiver to send data by asserting RTS low. The request is accepted

when CTS is returned low.

FCC1: Media Independent Interface Carrier Sense

Asserted by an external fast Ethernet PHY to indicate activity on the

cable.

PA29

FCC1: TXSOC

UTOPIA master

FCC1: TX_ER

MII

Output

FCC1: UTOPIA Transmit Start of Cell

Asserted by the MSC8103 (UTOPIA master PHY) when TXD[0–7]

contains the first valid byte of the cell.

FCC1: Media Independent Interface Transmit Error

Asserted by the MSC8103 to force propagation of transmit errors.

PA28

FCC1: RXENB

UTOPIA master

FCC1: RXENB

UTOPIA slave

FCC1: TX_EN

MII

Output

Input

Output

FCC1: UTOPIA Master Receive Enable

Asserted by the MSC8103 (UTOPIA master PHY) to indicate that

RXD[0–7] and RXSOC are to be sampled at the end of the next cycle.

RXD[0–7] and RXSOC are enabled only in cycles following those with

RXENB asserted.

FCC1: UTOPIA Master Receive Enable

Asserted by an external PHY to indicate that RXD[0–7] and RXSOC is to

be sampled at the end of the next cycle. RXD[0–7] and RXSOC are

enabled only in cycles following those with RXENB asserted.

FCC1: Media Independent Interface Transmit Enable

Asserted by the MSC8103 when transmitting data.

MSC8103 Datasheet(PDF) 20 Page - Freescale Semiconductor, Inc

MSC8103 Datasheet(HTML) 20 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL