TMS320DM647 datasheet(42/182 Pages) TI

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3.2.5

KEY_REG (write protection)

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372B – MAY 2007 – REVISED APRIL 2008

www.ti.com

Table 3-6. Default Master Priorities

MASTER

DEFAULT PRIORITY

EDMA3TC0

0 (EDMA CC QUEPRI Register)

EDMA3TC1

0 (EDMA CC QUEPRI Register)

EDMA3TC2

0 (EDMA CC QUEPRI Register)

EDMA3TC3

0 (EDMA CC QUEPRI Register)

64x+_DMAP

7 (C64x+ MDMAARBE.PRI Register bit field)

64x+_CFGP

1 (C64x+ MDMAARBE.PRI Register bit field)

Ethernet Subsystem

3 (PRI_ALLOC register)

VLYNQ

4 (PRI_ALLOC register)

UHPI

4 (PRI_ALLOC register)

PCI

4 (PRI_ALLOC register)

VICP

5 (PRI_ALLOC register)

Figure 3-4. Priority Allocation Register (PRI_ALLOC)

Reserved

R-0000000000001000

Reserved

VICP

VLYNQ

HOST

Ethernet Subsystem

R-0000

R/W-101

R/W-100

R/W-011

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

KEY_REG protects against accidental writes to certain system configuration registers. The complete set of

registers protected by the KEY_REG is:

• PINMUX

• BOOTCFG

• PRI_ALLOC

• CFGPLL

• CFGRX0

• CFGTX0

• CFGRX1

• CFGTX1

• MAC_ADDR_RW0

• MAC_ADDR_RW1

Writes to these registers are locked/blocked by default. To enable writes to these registers, write

0xADDDECAF to the KEY_REG. After enabling writes to protected registers by doing the above, the

Figure 3-5. KEY_REG

KEY_REG

W-0x00000000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Device Configuration

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