TMS320DM647 datasheet(95/182 Pages) TI

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6.9.3

DDR2 Interface

6.9.3.1 DDR2 Interface Schematic

6.9.3.2 Compatible JEDEC DDR2 Devices

6.9.3.3 PCB Stackup

TMS320DM647/TMS320DM648

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SPRS372B – MAY 2007 – REVISED APRIL 2008

Table 6-27. DDR2 Memory Controller Registers

HEX ADDRESS RANGE

ACRONYM

0x7800 0000

MIDR

DDR2 Memory Controller Module and Revision Register

0x7800 0004

DMCSTAT

DDR2 Memory Controller Status Register

0x7800 0008

SDCFG

DDR2 Memory Controller SDRAM Configuration Register

0x7800 000C

SDRFC

DDR2 Memory Controller SDRAM Refresh Control Register

0x7800 0010

SDTIM1

DDR2 Memory Controller SDRAM Timing 1 Register

0x7800 0014

SDTIM2

DDR2 Memory Controller SDRAM Timing 2 Register

0x7800 0018

Reserved

0x7800 0020

BPRIO

DDR2 Memory Controller Burst Priority Register

0x7800 0024 - 0x7800 004C

Reserved

0x7800 0050 - 0x7800 0078

Reserved

0x7800 007C - 0x7800 00BC

Reserved

0x7800 00C0 - 0x7800 00E0

Reserved

0x7800 00E4

DMCCTL

DDR2 Memory Controller Control Register

0x7800 00E8 - 0x7800 00FC

Reserved

0x7800 0100 - 0x7FFF FFFF

Reserved

This section provides the timing information for the DDR2 interface as a PCB design and manufacturing

specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,

and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need

for a complex timing closure process. For more information regarding guidelines for using this DDR2

specification, Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification (SPRAAV0).

Figure 6-12 shows the DDR2 interface schematic for a x32 DDR2 memory system. The x16 DDR2 system

schematic shown in Figure 6-13 is identical except that the high word DDR2 device is deleted.

Table 6-28 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.

Generally, the DDR2 interface is compatible with x16 DDR2-533 speed grade DDR2 devices.

Table 6-28. Compatible JEDEC DDR2 Devices

NO.

PARAMETER

MIN

MAX

UNIT

JEDEC DDR2 Device Speed Grade(1)

DDR2-533

JEDEC DDR2 Device Bit Width

x16

Bits

JEDEC DDR2 Device Count(2)

Devices

JEDEC DDR2 Device Ball Count(3)

Balls

(1)

Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility.

(2)

One DDR2 device is used for 16-bit DDR2 memory system. Two DDR2 devices are used for 32-bit DDR2 memory system.

(3)

92 ball devices retained for legacy support. New designs will migrate to 84 ball DDR2 devices. Electrically, the 92 and 84 ball DDR2

devices are the same.

The minimum stackup required for routing the DM647 is a six layer stack as shown in Table 6-29.

Additional layers may be added to the PCB stack up to accommodate other circuity or to reduce the size

of the PCB footprint.

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