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AS3722 Datasheet(PDF) 71 Page - ams-OSRAM AG

Part # AS3722
Description  Multi-Phase DCDC Controller PMIC
PDF  199 Pages
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Manufacturer  AMSOSRAM [ams-OSRAM AG]
Direct Link  https://ams-osram.com/
Logo AMSOSRAM - ams-OSRAM AG

AS3722 Datasheet(HTML) 71 Page - ams-OSRAM AG

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Page 70
ams Datasheet
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[v1-01] 2015-Sep-07
AS3722 − Detailed Descriptions- System Functions
Figure 66:
OC_PG Timing Diagram
OC_PG Timing Diagram: Shows the signal timing of the overcurrent-power-good output.
Supervisor
The PMIC has a build in over-temperature protection, which
could be switched off with the serial interface signal
temp_pmc_on (enabled by default; it is not recommended to
disable the over-temperature protection).
Temperature Supervision
The chip has three signals for the serial interface:
ov_temp_alarm0, ov_temp_alarm1 and ov_temp_shutdown.
The flags ov_temp_alarm0/1 are automatically reset if the
over-temperature condition is removed, whereas
ov_temp_shutdown has to be reset by the serial interface with
the signal rst_ov_temp_shutdown.
If the flag ov_temp_shutdown is set, an automatic reset of the
complete chip is initiated. The chip will only start-up when the
temperature falls below the Talarm0 level (including hysteresis).
The flag ov_temp_shutdown is not affected by this reset cycle
allowing the software to detect the reason for this unexpected
shutdown:
A similar supervision is done for the power-stage dies. The
over-temperature alarm flag (temp_sdX_alarm)is set, when a
sub die reaches the alarm level. The over-temperature alarm
flag is set anyway and cleared when the temperature falls below
the threshold. When reaching the shutdown level an automatic
reset (can be masked) of the AS3722 is initiated. The
sd0_on
Vout
Tstart = 250usec max.
OC_PG
10nsec delay
OC_PG>90usec high
(typ. 120usec).
AC_OK or
GPIO3,4,5
if enalbed
100nsec delay done in analog
sd0_vsel
pg_vmask_time=4/8usec
mask
10nsec delay
100nsec
delay done in analog
sd0_lv or ov_curr



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