AS1170 datasheet(11/53 Pages) AMSOSRAM

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AS1170

Electrical characteristics

Datasheet

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5.1

I²C specifications

Table 5: I²C specifications

Symbol

Parameter

Condition

Min

Typ.

Max

Unit

I²C mode timings

– see Figure 3

fSCLK

SCL clock frequency

1 / tTIMEOUT

400

kHz

tBUF

Bus free time between a

STOP and START condition

1.3

µs

tHD:STA

Hold time (repeated) START

Condition (7)

0.6

µs

tLOW

LOW period of SCL clock

1.3

µs

tHIGH

HIGH period of SCL clock

0.6

µs

tSU:STA

Setup time for a repeated

START condition

0.6

µs

tHD:DAT

Data hold time (8)

0.9

µs

tSU:DAT

Data setup time (9)

100

Rise time of both SDA and

SCL signals

20 + 0.1CB

300

Fall time of both SDA and

SCL signals

20 + 0.1CB

300

tSU:STO

Setup time for STOP

condition

0.6

µs

Capacitive load for each bus

line

CB - total

capacitance of one

bus line in pF

400

CI/O

I/O capacitance (SDA, SCL)

(1) For VBAT=4.5 V, SCL=1.8 V, SDA=1.8 V maximum ISTANBY is <16 µA.

(2) To improve efficiency at low output currents, the active part of the internal switching transistor PMOS is reduced in size to 1/5

its original size. This reduces the current required to drive the PMOS transistor and therefore improves overall efficiency at

low output currents.

(3) The maximum current driving capability depends on supply voltage VVIN, LED forward voltage and coil peak current limit.

(4) Due to slope compensation of the current limit, ILIMIT changes with duty cycle – see Figure 17.

(5) The logic input levels VIH and VIL allow for 1.2 V or 1.8 V supplied driving circuit.

(6) A pulldown current of 36

µA is equal to a pulldown resistor of 42 kΩ at 1.5 V.

(7) After this period, the first clock pulse is generated.

(8) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

(9) A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT = to 250 ns must then be met. This is

automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW

period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250 ns before the SCL

line is released.

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